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21. 发明申请

US20150241876A1 Clustering for Prediction Models in Process Control and for Optimal Dispatching 审中-公开
标题翻译：过程控制和最优调度中预测模型的聚类
公开(公告)号：US20150241876A1
公开(公告)日：2015-08-27
申请号：US14706768
申请日：2015-05-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung Cheng Ko , Tzu-Yu Wang , Kewei Zuo , Kuan Teng Lo , Chien Rhone Wang , Chih-Wei Lai
IPC分类号： G05B19/418
CPC分类号： G05B19/41885 , G05B17/02 , G05B2219/45032
摘要： A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.
摘要翻译：第一实施例是一种用于半导体处理控制的方法，其包括基于处理数据将处理级的处理工具集群到工具集群中，并且基于工具集群形成用于处理半导体晶片的预测模型。第二实施例是一种用于半导体处理控制的方法，包括提供第一级工具集群和第二级工具集群之间的集群路由，为每个集群路由分配比较优化等级，以及调度晶片的处理。比较优化排名确定了哪些集群路由提供高晶圆处理均匀性。此外，需要高晶圆处理均匀性的晶片被调度为沿着具有高比较优化等级的一个集群路由进行处理，该优先等级标识一个集群路由以具有最高的晶片处理均匀性，并且不需要高晶片处理均匀性的晶片是计划沿着另一个集群路由处理。

22. 发明授权

US09002504B2 Method of wafer system interlock for the protection of equipment and product in semiconductor processing bridge tool 有权
标题翻译：晶圆系统联锁方法，用于保护半导体加工桥梁工具中的设备和产品
公开(公告)号：US09002504B2
公开(公告)日：2015-04-07
申请号：US13797460
申请日：2013-03-12
申请人： Kawasaki Robotics (USA), Inc.
发明人： Thomas Miu , Shinya Kitano , Simon Jeyapalan , Ming Zeng , Avish A. Bharwani
IPC分类号： G06F7/00 , G06F19/00 , G05B19/04 , B25J9/16
CPC分类号： G05B19/401 , G05B2219/37345 , G05B2219/45032 , Y10S901/02
摘要： The present disclosure is directed to methods and systems for evaluating wafer size handling capabilities of wafer handling robots and wafer stations in a wafer processing environment. In one embodiment, a method is provided in which size parameters for each of one or more wafer stations and one or more robot hands of a wafer handling robot are set based on user input. A user command identifying a desired robot hand and a desired wafer station is received. A first size parameter of the desired robot hand is compared to a second size parameter of the desired wafer station. If the first size parameter is equal to the second size parameter, or if the second size parameter is an all-size parameter, the user command is executed. If the first size parameter is not equal to the second size parameter, an error is generated.
摘要翻译：本公开涉及用于在晶片处理环境中评估晶片处理机器人和晶圆台的晶片尺寸处理能力的方法和系统。在一个实施例中，提供了一种方法，其中基于用户输入来设置晶片处理机器人的一个或多个晶片台和一个或多个机器人手中的每一个的尺寸参数。接收识别所需机器人手和期望的晶片台的用户命令。将期望的机器人手的第一尺寸参数与期望的晶片台的第二尺寸参数进行比较。如果第一个尺寸参数等于第二个尺寸参数，或者如果第二个尺寸参数是全尺寸参数，则执行用户命令。如果第一个尺寸参数不等于第二个尺寸参数，则会生成错误。

23. 发明授权

US08868233B2 Control apparatus, a substrate treating method, a substrate treating system, a method of operating a substrate treating system, a load port control apparatus, and a substrate treating system having the load port control apparatus 有权
标题翻译：控制装置，基板处理方法，基板处理系统，操作基板处理系统的方法，负载端口控制装置和具有负载端口控制装置的基板处理系统
公开(公告)号：US08868233B2
公开(公告)日：2014-10-21
申请号：US13541345
申请日：2012-07-03
申请人： Hideki Shibata
发明人： Hideki Shibata
IPC分类号： G06F7/00 , H01L21/67 , H01L21/677 , G05B19/418
CPC分类号： H01L21/67276 , G05B19/41865 , G05B2219/45032 , H01L21/67736 , Y02P90/20
摘要： A control apparatus in a substrate treating system with a substrate treating apparatus having a physical load port for receiving pods for storing substrates, and a carrier transport system for transporting the pods to and from the physical load port. The control apparatus includes a virtual load port control device for allotting a virtual load port to the physical load port, and instructing the carrier transport system to perform a transporting operation to and from the virtual load port on an assumption that the virtual load port really exists.
摘要翻译：具有基板处理装置的基板处理系统中的控制装置，该基板处理装置具有物理负载端口，用于接收用于存储基板的容器;以及载体传输系统，用于将物理空间输送到物理负载端口。控制装置包括：虚拟负载端口控制装置，用于将虚拟负载端口分配给物理负载端口，并且指示运营商传输系统在虚拟负载端口真实存在的假设下执行与虚拟负载端口的传输操作。

24. 发明授权

US06304791B1 Method for controlling semiconductor equipment interlocked with a host computer 失效
标题翻译：用于控制与主机互锁的半导体设备的方法
公开(公告)号：US06304791B1
公开(公告)日：2001-10-16
申请号：US09137935
申请日：1998-08-21
申请人： Sung-geun Kim
发明人： Sung-geun Kim
IPC分类号： G06F1900
CPC分类号： G05B19/4184 , G05B2219/45032 , G05B2219/50106 , Y02P90/14
摘要： A method for controlling semiconductor fabrication equipment prevents an operator from accidently operating a piece of equipment which is in an interlocked state, since a host computer automatically stores information on any interlocked piece of equipment, and rechecks that information before allowing any product to be introduced into a piece of equipment. Optimal process conditions for each process are registered in the host computer. The registered optimal process condition is compared with process data reported from each piece of equipment. If it is determined that the reported data are in the range of the optimal process conditions in view of the comparison, it is then determined whether or not the reported data also satisfy a specific rule registered in the host computer. If it is determined that the reported data satisfy the specific rule, the process continues. Otherwise, if it is determined that the reported data do not satisfy the specific rule, the equipment and a tracking module of the host computer are simultaneously interlocked and the interlocking is automatically saved in the host computer. The process is stopped until the process failure is solved.
摘要翻译：一种用于控制半导体制造设备的方法防止操作者意外地操作处于联锁状态的设备，因为主计算机自动存储关于任何互锁的设备的信息，并且在允许任何产品被引入之前重新检查该信息一件设备。在主计算机中注册每个进程的最佳处理条件。将注册的最佳工艺条件与每台设备报告的过程数据进行比较。如果根据比较确定所报告的数据在最佳处理条件的范围内，则确定所报告的数据是否也满足在主计算机中登记的特定规则。如果确定报告的数据满足特定规则，则该过程继续。否则，如果确定报告的数据不满足特定规则，则主机的设备和跟踪模块同时互锁，并且互锁被自动保存在主计算机中。该过程停止，直到过程失败被解决。

25. 发明授权

US10073444B2 Petri net-based optimal one-wafer cyclic scheduling of treelike hybrid multi-cluster tools 有权
公开(公告)号：US10073444B2
公开(公告)日：2018-09-11
申请号：US14919720
申请日：2015-10-21
申请人： Macau University of Science and Technology
发明人： Naiqi Wu , Fajun Yang , Yan Qiao , Mengchu Zhou
IPC分类号： G05B19/41 , G05B19/418
CPC分类号： G05B19/4187 , G05B2219/31429 , G05B2219/45032 , Y02P90/205 , Y10S901/02 , Y10S901/41
摘要： Since single and dual-arm tools behave differently, it is difficult to coordinate their activities in a hybrid multi-cluster tool that is composed of both single- and dual-arm tools. Aiming at finding an optimal one-wafer cyclic schedule for a treelike hybrid multi-cluster tool whose bottleneck tool is process-bound, the present work extends a resource-oriented Petri net to model such system. By the developed Petri net model, to find a one-wafer cyclic schedule is to determine robot waiting times. By doing so, it is shown that, for any treelike hybrid multi-cluster tool whose bottleneck tool is process-bound, there is always a one-wafer cyclic schedule. Then, computationally efficient algorithms are developed to obtain the minimal cycle time and the optimal one-wafer cyclic schedule. Examples are given to illustrate the developed method.

26. 发明授权

US10054938B2 Clustering for prediction models in process control and for optimal dispatching 有权
公开(公告)号：US10054938B2
公开(公告)日：2018-08-21
申请号：US14706768
申请日：2015-05-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung Cheng Ko , Tzu-Yu Wang , Kewei Zuo , Kuan Teng Lo , Chien Rhone Wang , Chih-Wei Lai
IPC分类号： G05B17/02 , G05B15/02 , G05B19/418
CPC分类号： G05B19/41885 , G05B17/02 , G05B2219/45032
摘要： A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

27. 发明授权

US09966247B2 Control system and control method for component mounting machine 有权
公开(公告)号：US09966247B2
公开(公告)日：2018-05-08
申请号：US14425151
申请日：2012-09-06
申请人： Yukinori Nakayama , Hideyasu Takamiya
发明人： Yukinori Nakayama , Hideyasu Takamiya
IPC分类号： B23P19/00 , H01L21/02 , H01L21/67 , H01L23/00 , G05B19/418
CPC分类号： H01L21/02 , G05B19/418 , G05B2219/45032 , H01L21/67144 , H01L24/75 , H01L2224/75745 , H01L2224/759 , Y10T29/53178
摘要： A wafer component supply device supplying a wafer component and a feeder, such as a tape feeder supplying an electronic component, are set in a component mounting machine. When the wafer component is to be inverted and mounted on a circuit substrate, the wafer component supply device allows the wafer component present on an inverted supply head to be sucked by a mounting head of the component mounting machine at a position where the supply head and a stage are moved down by a vertical movement mechanism. An order of an operation for inverting the wafer component and mounting the wafer component on the circuit substrate and an operation for mounting the feeder component on the circuit substrate is set so that the supply head and the mounting head do not interfere with each other; and an operation for moving down the supply head and the stage, allowing the wafer component to be sucked by the supply head, and inverting the wafer component is performed so as to overlap with an operation for sucking and mounting the feeder component by the mounting head.

28. 发明申请

US20170018444A1 SUBSTRATE TRANSFER APPARATUS, SUBSTRATE TRANSFER METHOD, AND NON-TRANSITORY STORAGE MEDIUM 审中-公开
标题翻译：基板传输设备，基板传输方法和非接收式存储介质
公开(公告)号：US20170018444A1
公开(公告)日：2017-01-19
申请号：US15278155
申请日：2016-09-28
申请人： Tokyo Electron Limited
发明人： Tokutarou HAYASHI , Yuichi DOUKI , Hiromitsu MAEJIMA
IPC分类号： H01L21/67 , G05B19/418 , H01L21/68 , G05D3/12 , H01L21/677
CPC分类号： H01L21/67259 , G05B19/4189 , G05B2219/45032 , G05B2219/45051 , G05D3/125 , H01L21/67742 , H01L21/681
摘要： A substrate transfer apparatus to transfer a circular substrate provided with a cutout at an edge portion thereof, includes: a sensor part including three light source parts applying light to positions different from one another at the edge portion, and three light receiving parts paired with the light source parts; and a drive part for moving the substrate holding part, wherein the three light source parts apply light to the light receiving parts so that whether or not a detection range of the sensor part overlaps with the cutout of the substrate is determined on the basis of an amount of received light by each light receiving part, and when it is determined that there is an overlap at any position, positions of the edge portion of the substrate are further detected with the position of the substrate displaced with respect to the sensor part.
摘要翻译：一种用于在其边缘部分传送设置有切口的圆形基板的基板传送装置，包括：传感器部分，包括三个光源部分，该光源部分将光施加到边缘部分处彼此不同的位置，以及三个光接收部分光源部件; 以及用于移动所述基板保持部的驱动部，其中，所述三个光源部向所述受光部施加光，使得所述传感器部的检测范围是否与所述基板的切口重叠，基于每个光接收部分的接收光量，并且当确定在任何位置处存在重叠时，基板的边缘部分的位置被进一步检测到基板相对于传感器部分移位的位置。

29. 发明授权

US09466673B2 Complementary metal-oxide silicon having silicon and silicon germanium channels 有权
公开(公告)号：US09466673B2
公开(公告)日：2016-10-11
申请号：US15076871
申请日：2016-03-22
申请人： International Business Machines Corporation
发明人： Gen P. Lauer , Isaac Lauer , Alexander Reznicek , Jeffrey W. Sleight
IPC分类号： H01L21/00 , H01L29/10 , H01L21/84 , H01L21/8238 , H01L29/161 , H01L21/02 , H01L21/324 , H01L21/3065
CPC分类号： H01L29/1054 , G05B19/19 , G05B2219/45032 , H01L21/02532 , H01L21/02639 , H01L21/3065 , H01L21/324 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/1203 , H01L29/0649 , H01L29/161 , H01L29/7849 , H01L29/785
摘要： A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

30. 发明申请

US20160211327A1 COMPLEMENTARY METAL-OXIDE SILICON HAVING SILICON AND SILICON GERMANIUM CHANNELS 有权
公开(公告)号：US20160211327A1
公开(公告)日：2016-07-21
申请号：US15076871
申请日：2016-03-22
申请人： International Business Machines Corporation
发明人： Gen P. Lauer , Isaac Lauer , Alexander Reznicek , Jeffrey W. Sleight
IPC分类号： H01L29/10 , H01L21/8238 , H01L21/3065 , H01L21/02 , H01L21/324 , H01L21/84 , H01L29/161
CPC分类号： H01L29/1054 , G05B19/19 , G05B2219/45032 , H01L21/02532 , H01L21/02639 , H01L21/3065 , H01L21/324 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/1203 , H01L29/0649 , H01L29/161 , H01L29/7849 , H01L29/785
摘要： A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

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