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21. 发明申请

US20170325751A1 BLOOD PRESSURE MEASUREMENT APPARATUS AND BLOOD PRESSURE MEASUREMENT METHOD 审中-公开
公开(公告)号：US20170325751A1
公开(公告)日：2017-11-16
申请号：US15666904
申请日：2017-08-02
申请人： MegaChips Corporation
发明人： Handa CHEN
IPC分类号： A61B5/00 , A61B5/021 , A61B5/024
CPC分类号： A61B5/7278 , A61B5/02108 , A61B5/02416 , A61B5/7225 , A61B5/7235 , A61B5/742
摘要： A blood pressure measurement apparatus includes circuitry configured to: detect a pulse of a subject, and obtain a photoplethysmography signal; and obtain estimated blood pressure of the subject based on the photoplethysmography signal. The circuitry receives parameter information, generates time information based on the photoplethysmography signal, applies a blood pressure estimation equation to the time information and the parameter information to calculate the estimated blood pressure, receives basic blood pressure information for the subject and the time information, and performs learning processing of applying a learning operational equation to statistical time information, which is obtained by performing statistical processing on the time information, and the basic blood pressure information to update the parameter information.

22. 发明授权

US09749637B2 Transcoder for conversion by obtaining a period conversion factor from a bit rate ratio 有权
公开(公告)号：US09749637B2
公开(公告)日：2017-08-29
申请号：US14706126
申请日：2015-05-07
申请人： MegaChips Corporation
发明人： Hiromu Hasegawa , Nobuyuki Takasu , Makoto Saito
IPC分类号： H04N7/12 , H04N19/146 , H04N19/177 , H04N19/40 , H04N19/124
CPC分类号： H04N19/146 , H04N19/114 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/15 , H04N19/157 , H04N19/162 , H04N19/169 , H04N19/177 , H04N19/40 , H04N19/61
摘要： If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

23. 发明申请

US20170170835A1 FREQUENCY CALIBRATION CIRCUIT AND FREQUENCY CALIBRATION METHOD 审中-公开
公开(公告)号：US20170170835A1
公开(公告)日：2017-06-15
申请号：US15374008
申请日：2016-12-09
申请人： MegaChips Corporation
发明人： Hidetoshi Tsubota , Hideyuki Sato
IPC分类号： H03L7/099 , H03B5/32 , H03L1/02
CPC分类号： H03L7/0992 , H03B5/32 , H03B5/366 , H03L1/022 , H03L1/028 , H03L7/099 , H03L7/18 , H03L2207/50
摘要： In the frequency calibration circuit, the digital phase-locked-loop circuit repeats a calibration operation involving outputting the digital control signal corresponding to a time difference between the first clock signal which is input from the first oscillator and has a first frequency accuracy, and the second clock signal which is input from the second oscillator and has a second frequency accuracy lower than the first frequency accuracy, changing the capacitance of the discrete type capacitor bank in accordance with the digital control signal using the second oscillator as a digital control oscillator, and changing an oscillation frequency of the second clock signal in accordance with the capacitance of the discrete type capacitor bank, thereby calibrating a phase of the second clock signal to a phase of the first clock signal.

24. 发明授权

US09661333B2 Image processor for code amount control 有权
公开(公告)号：US09661333B2
公开(公告)日：2017-05-23
申请号：US13522122
申请日：2010-11-29
申请人： Toshimitsu Tatsuka , Hiromu Hasegawa , Takeaki Komuro , Masato Yamada
发明人： Toshimitsu Tatsuka , Hiromu Hasegawa , Takeaki Komuro , Masato Yamada
IPC分类号： H04N11/04 , H04N7/12 , H04N19/174 , H04N19/147 , H04N19/196 , H04N19/149 , H04N19/61 , H04N19/124
CPC分类号： H04N19/174 , H04N19/124 , H04N19/147 , H04N19/149 , H04N19/196 , H04N19/61
摘要： An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.

25. 发明申请

US20170134755A1 IMAGE PROCESSOR 审中-公开
公开(公告)号：US20170134755A1
公开(公告)日：2017-05-11
申请号：US15405534
申请日：2017-01-13
申请人： MegaChips Corporation
发明人： Naotsugu YAMAMURA , Akira Okamoto , Nobuyuki Takasu
IPC分类号： H04N19/65 , H04N19/44 , H04N19/105
CPC分类号： H04N19/65 , H04N19/105 , H04N19/164 , H04N19/172 , H04N19/44
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

26. 发明授权

US09647642B2 Clock phase adjustment mechanism of a ring oscillator using a phase control signal 有权
公开(公告)号：US09647642B2
公开(公告)日：2017-05-09
申请号：US14809920
申请日：2015-07-27
申请人： MegaChips Corporation
发明人： Hidetoshi Tsubota
IPC分类号： H03K3/012 , H03K3/03 , H03K3/356 , H03K5/04 , H03K5/131 , H03K5/14 , H03K5/151
CPC分类号： H03K3/012 , H03K3/0322 , H03K3/356182 , H03K5/04 , H03K5/131 , H03K5/14 , H03K5/151
摘要： A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a ring shape, and a phase controller to control an output of a differential inverter circuit which belongs to a second group, in a first state or a second state, for a predetermined time period. The differential inverter circuit which belongs to the second group is distinct from a differential inverter circuit which belongs to a first group. The differential inverter circuit which belongs to the second group, in the first state, outputs a first logic signal from a first differential output terminal and outputs a second logic signal from a second differential output terminal. Further, the differential inverter circuit which belongs to the second group, in the second state, outputs the second logic signal from the first differential output terminal and outputs the first logic signal from the second differential output terminal.

27. 发明授权

US09641867B2 Image processor 有权
公开(公告)号：US09641867B2
公开(公告)日：2017-05-02
申请号：US14919979
申请日：2015-10-22
申请人： MegaChips Corporation
发明人： Naotsugu Yamamura , Akira Okamoto , Nobuyuki Takasu
IPC分类号： G06K9/36 , G06K9/46 , H04N19/65 , H04N19/44 , H04N19/105 , H04N19/172 , H04N19/164
CPC分类号： H04N19/65 , H04N19/105 , H04N19/164 , H04N19/172 , H04N19/44
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

28. 发明申请

US20170103501A1 IMAGE PROCESSOR 有权
公开(公告)号：US20170103501A1
公开(公告)日：2017-04-13
申请号：US15388959
申请日：2016-12-22
申请人： MegaChips Corporation
发明人： Hiroki NAKAMORI , Takuya SAWADA , Hideki DAIAN
IPC分类号： G06T5/00
CPC分类号： G06T5/002 , G06T2207/10004 , G06T2207/20012 , G06T2207/20021 , G06T2207/20192 , H04N19/124 , H04N19/176 , H04N19/60
摘要： A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image.

29. 发明申请

US20170060460A1 MEMORY CONTROLLER 审中-公开
标题翻译：内存控制器
公开(公告)号：US20170060460A1
公开(公告)日：2017-03-02
申请号：US15242713
申请日：2016-08-22
申请人： MegaChips Corporation
发明人： Takahiko Sugahara , Hiromu Yutani , Hajime Yoshimura
IPC分类号： G06F3/06 , G06F12/14
CPC分类号： G06F3/0623 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/14 , G06F13/161 , G06F13/1631 , G06F2212/1052 , G06F2212/214
摘要： An object of the present invention is to provide a technique that makes it difficult to fabricate an illegal duplicate of a semiconductor storage apparatus. In a memory controller, an address acquisition unit acquires a latency-related designated address. The latency-related designated address is an address in the semiconductor memory storing data to be transmitted with the minimum latency upon reception of a read command, and is identical with an address held by a host. A pre-acquisition unit reads the data for the latency-related designated address from the semiconductor memory and stores it in the buffer. A comparator compares the address included in the read command to the latency-related designated address. Depending on the result of the comparison by the comparator, a transmission control unit transmits the data stored in the buffer to the host at the time point of completion of a minimum latency.
摘要翻译：本发明的目的是提供一种难以制造半导体存储装置的非法副本的技术。在存储器控制器中，地址获取单元获取等待时间相关的指定地址。等待时间相关指定地址是存储在接收到读命令时以最小等待时间发送的数据的半导体存储器中的地址，并且与由主机保持的地址相同。预采集单元从半导体存储器读取与延迟相关的指定地址的数据，并将其存储在缓冲器中。比较器将读取命令中包含的地址与等待时间相关的指定地址进行比较。根据比较器的比较结果，传输控制单元在完成最小等待时间的时间点将存储在缓冲器中的数据发送给主机。

30. 发明授权

US09553595B2 Clock operation method and circuit 有权
标题翻译：时钟操作方法和电路
公开(公告)号：US09553595B2
公开(公告)日：2017-01-24
申请号：US14614783
申请日：2015-02-05
申请人： MegaChips Corporation
发明人： Tomohiro Wanibuchi
IPC分类号： G06F1/10 , H03L7/18 , H03K5/153 , G06F1/08 , G06F1/12 , H03K23/66
CPC分类号： H03L7/18 , G06F1/08 , G06F1/10 , G06F1/12 , H03K5/153 , H03K23/66
摘要： In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.
摘要翻译：在时钟发生电路中，可变分频电路通过根据分频比设置信号划分源时钟来产生可变分频时钟。第一时钟同步电路产生与源时钟同步地从可变分频时钟延迟最大数量的时钟的第一延迟时钟，并将第一延迟时钟提供给控制电路。一个或多个第二时钟同步电路产生一个或多个第二延迟时钟，每个第二延迟时钟与源时钟同步地从可变分频时钟延迟最大时钟数，并将一个或多个第二延迟时钟中的每一个提供给每个一个或多个功能模块。

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