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1. 发明授权

US10455111B2 Encryption device, computer-readable recording medium, and encryption method 有权
公开(公告)号：US10455111B2
公开(公告)日：2019-10-22
申请号：US15472748
申请日：2017-03-29
申请人： MegaChips Corporation
发明人： Nobuyuki Takasu
IPC分类号： G06F21/00 , H04N1/32 , H04N1/44 , H04L9/06
摘要： An encryption circuit includes a fundamental vector generation circuit configured to generate a random number sequence for serving as a fundamental vector based on an initial vector, an image mask generation circuit configured to generate an image mask with a mask value set for each pixel in a region to be encrypted smaller than a frame size of the image, based on the fundamental vector and coordinate information for specifying the region to be encrypted, and an XOR operation circuit configured to compute an exclusive OR between each mask value of the image mask and each pixel value of the image data to generate encrypted image data.

2. 发明申请

US20160119648A1 IMAGE PROCESSOR 有权
标题翻译：图像处理器
公开(公告)号：US20160119648A1
公开(公告)日：2016-04-28
申请号：US14919979
申请日：2015-10-22
申请人： MegaChips Corporation
发明人： Naotsugu YAMAMURA , Akira Okamoto , Nobuyuki Takasu
IPC分类号： H04N19/65 , H04N19/423 , H04N19/44
CPC分类号： H04N19/65 , H04N19/105 , H04N19/164 , H04N19/172 , H04N19/44
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.
摘要翻译：在重新开始发送编码图像数据之后的最早的垂直同步时段中，第一参考图像确定电路确定使用紧邻垂直同步周期之前的垂直同步周期中产生的局部解码图像，其中在多个局部解码图像之间发生错误存储在第一DRAM中作为参考图像。在解码电路复位之后的最早的垂直同步时段中，第二参考图像确定电路确定使用在紧接在垂直同步周期之前的垂直同步周期中生成的解码图像，其中在存储在第二个 DRAM作为参考图像。

3. 发明授权

US10327009B2 Image processor 有权
公开(公告)号：US10327009B2
公开(公告)日：2019-06-18
申请号：US15405534
申请日：2017-01-13
申请人： MegaChips Corporation
发明人： Naotsugu Yamamura , Akira Okamoto , Nobuyuki Takasu
IPC分类号： G06K9/36 , G06K9/46 , H04N19/65 , H04N19/44 , H04N19/105 , H04N19/172 , H04N19/164
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

4. 发明授权

US09749637B2 Transcoder for conversion by obtaining a period conversion factor from a bit rate ratio 有权
公开(公告)号：US09749637B2
公开(公告)日：2017-08-29
申请号：US14706126
申请日：2015-05-07
申请人： MegaChips Corporation
发明人： Hiromu Hasegawa , Nobuyuki Takasu , Makoto Saito
IPC分类号： H04N7/12 , H04N19/146 , H04N19/177 , H04N19/40 , H04N19/124
CPC分类号： H04N19/146 , H04N19/114 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/15 , H04N19/157 , H04N19/162 , H04N19/169 , H04N19/177 , H04N19/40 , H04N19/61
摘要： If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

5. 发明申请

US20170134755A1 IMAGE PROCESSOR 审中-公开
公开(公告)号：US20170134755A1
公开(公告)日：2017-05-11
申请号：US15405534
申请日：2017-01-13
申请人： MegaChips Corporation
发明人： Naotsugu YAMAMURA , Akira Okamoto , Nobuyuki Takasu
IPC分类号： H04N19/65 , H04N19/44 , H04N19/105
CPC分类号： H04N19/65 , H04N19/105 , H04N19/164 , H04N19/172 , H04N19/44
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

6. 发明授权

US09641867B2 Image processor 有权
公开(公告)号：US09641867B2
公开(公告)日：2017-05-02
申请号：US14919979
申请日：2015-10-22
申请人： MegaChips Corporation
发明人： Naotsugu Yamamura , Akira Okamoto , Nobuyuki Takasu
IPC分类号： G06K9/36 , G06K9/46 , H04N19/65 , H04N19/44 , H04N19/105 , H04N19/172 , H04N19/164
CPC分类号： H04N19/65 , H04N19/105 , H04N19/164 , H04N19/172 , H04N19/44
摘要： In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

7. 发明授权

US09532075B2 Image processor 有权
标题翻译：图像处理器
公开(公告)号：US09532075B2
公开(公告)日：2016-12-27
申请号：US14219148
申请日：2014-03-19
申请人： MegaChips Corporation
发明人： Takeaki Komuro , Nobuyuki Takasu , Kazuhiro Saito
IPC分类号： H04N19/13 , H04N19/82 , H04N19/70 , H04N19/42
CPC分类号： H04N19/82 , H04N19/13 , H04N19/42 , H04N19/70
摘要： The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.
摘要翻译：图像处理器包括将输入值X近似乘以1/3的¼乘法器电路。 ¼乘法器电路包括通过循环重复执行预定操作的环路操作电路，以及在环路操作电路中设置所需数量的环路的设置电路。环路运算电路包括接收输入值的输入的寄存器，在从寄存器输出的值上向右移位2位的位移电路，以及将输入值和值相加的加法电路从位移电路输出，并将附加值输入到寄存器。

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