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1. 发明申请

US20170060460A1 MEMORY CONTROLLER 审中-公开
标题翻译：内存控制器
公开(公告)号：US20170060460A1
公开(公告)日：2017-03-02
申请号：US15242713
申请日：2016-08-22
申请人： MegaChips Corporation
发明人： Takahiko Sugahara , Hiromu Yutani , Hajime Yoshimura
IPC分类号： G06F3/06 , G06F12/14
CPC分类号： G06F3/0623 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F12/14 , G06F13/161 , G06F13/1631 , G06F2212/1052 , G06F2212/214
摘要： An object of the present invention is to provide a technique that makes it difficult to fabricate an illegal duplicate of a semiconductor storage apparatus. In a memory controller, an address acquisition unit acquires a latency-related designated address. The latency-related designated address is an address in the semiconductor memory storing data to be transmitted with the minimum latency upon reception of a read command, and is identical with an address held by a host. A pre-acquisition unit reads the data for the latency-related designated address from the semiconductor memory and stores it in the buffer. A comparator compares the address included in the read command to the latency-related designated address. Depending on the result of the comparison by the comparator, a transmission control unit transmits the data stored in the buffer to the host at the time point of completion of a minimum latency.
摘要翻译：本发明的目的是提供一种难以制造半导体存储装置的非法副本的技术。在存储器控制器中，地址获取单元获取等待时间相关的指定地址。等待时间相关指定地址是存储在接收到读命令时以最小等待时间发送的数据的半导体存储器中的地址，并且与由主机保持的地址相同。预采集单元从半导体存储器读取与延迟相关的指定地址的数据，并将其存储在缓冲器中。比较器将读取命令中包含的地址与等待时间相关的指定地址进行比较。根据比较器的比较结果，传输控制单元在完成最小等待时间的时间点将存储在缓冲器中的数据发送给主机。

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