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21. 发明申请

US20150325565A1 Composite Semiconductor Device with Multiple Threshold Voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US20150325565A1
公开(公告)日：2015-11-12
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L27/02 , H01L29/08 , H01L21/265 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/10
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

22. 发明授权

US09117841B2 Mergeable semiconductor device with improved reliability 有权
标题翻译：合并半导体器件具有可靠性提高
公开(公告)号：US09117841B2
公开(公告)日：2015-08-25
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

23. 发明授权

US08853780B2 Semiconductor device with drain-end drift diminution 有权
标题翻译：漏极端漂移的半导体器件减少
公开(公告)号：US08853780B2
公开(公告)日：2014-10-07
申请号：US13465761
申请日：2012-05-07
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

24. 发明申请

US20140209988A1 NONVOLATILE MEMORY BITCELL 审中-公开
标题翻译：非易失性存储器BITCELL
公开(公告)号：US20140209988A1
公开(公告)日：2014-07-31
申请号：US13756248
申请日：2013-01-31
申请人： Xin Lin , Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/088
CPC分类号： H01L29/66825 , H01L27/11558 , H01L29/7881
摘要： A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.
摘要翻译：具有单个多晶硅存储单元的多时间可编程非易失性存储器件包括选择晶体管和位单元晶体管。位单元晶体管具有不对称配置的源极，漏极和沟道区域，包括不对称配置的源极体和漏极 - 体部结。与漏 - 体结相比，源 - 体结的杂质浓度梯度更为平缓，可以显着提高程序的干扰免疫力。位单元晶体管栅极可以连接到耦合电容器的电极，但是可以以浮置或欧姆隔离的方式。位单元的浮动栅极由介电层保护，以便潜在地改善数据保持。

25. 发明申请

US20140203358A1 SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF 有权
标题翻译：具有增强3D修复功能的半导体器件
公开(公告)号：US20140203358A1
公开(公告)日：2014-07-24
申请号：US13748076
申请日：2013-01-23
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移源极和漏极区域。漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

26. 发明授权

US09041103B2 RESURF semiconductor device charge balancing 有权
标题翻译： RESURF半导体器件电荷平衡
公开(公告)号：US09041103B2
公开(公告)日：2015-05-26
申请号：US13781722
申请日：2013-02-28
申请人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
发明人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
IPC分类号： H01L29/772 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.
摘要翻译：即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻，和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的隔离墙和漂移区之间的电阻桥。该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置通过隔离壁耦合到掩埋层的漏极电压的百分比。

27. 发明授权

US08487398B2 Capacitor device using an isolated well and method therefor 有权
标题翻译：使用隔离井的电容器件及其方法
公开(公告)号：US08487398B2
公开(公告)日：2013-07-16
申请号：US12835900
申请日：2010-07-14
申请人： Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L21/70
CPC分类号： H01L29/94 , H01L29/66181
摘要： A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.
摘要翻译：半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。该装置可以方便地连接到边缘电容器。

28. 发明申请

US20140264724A1 DEEP TRENCH ISOLATION 有权
标题翻译：深层分离分离
公开(公告)号：US20140264724A1
公开(公告)日：2014-09-18
申请号：US13801514
申请日：2013-03-13
申请人： Xu Cheng , Daniel J. Blomberg , Zhihong Zhang , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/0638 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/763 , H01L21/82285 , H01L21/823878 , H01L21/8249 , H01L27/10876 , H01L29/0611 , H01L29/0649 , H01L29/1083 , H01L29/66272
摘要： An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
摘要翻译：集成半导体器件包括第一导电类型的衬底，位于衬底上的掩埋层，位于掩埋层的第一部分上方的隔离区域和位于隔离区域周围的隔离沟槽。穿透结构位于隔离沟槽的至少一部分周围。所述穿通结构包括所述掩埋层的第二部分，位于所述掩埋层的所述第二部分上方的第一区域，所述第一区域具有第二导电类型，以及位于所述第一区域上方的第二区域，所述第二区域具有第一种导电类型。

29. 发明授权

US08389366B2 Resurf semiconductor device charge balancing 有权
标题翻译： Resurf半导体器件电荷平衡
公开(公告)号：US08389366B2
公开(公告)日：2013-03-05
申请号：US12129840
申请日：2008-05-30
申请人： Won Gi Min , Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
发明人： Won Gi Min , Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/772
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).
摘要翻译：即使当主体（44,44'，84,84“），RESURF装置（40,60,80,80'，80”），例如LDMOS晶体管也通过小心的电荷平衡来增强击穿电压BVdss并导通电阻，）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且延伸通过相同的导电类型至少进入下面的主体区域（44,44'，84,84'）中的漂移区域（50,50'，90,90'），和/或（ii）将偏置Viso施加到周围的侧向掺杂隔离壁（102 ）和/或（iii）在所述隔离壁（102）和所述漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

30. 发明申请

US20090294849A1 RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING 有权
标题翻译： RESURF半导体器件充电平衡
公开(公告)号：US20090294849A1
公开(公告)日：2009-12-03
申请号：US12129840
申请日：2008-05-30
申请人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
发明人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L23/58
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).
摘要翻译：即使在主体（44,44'，84,84）中，分解电压BVdss被增强，并且RESURF器件（40,60,80,80'，80“）中的导通电阻降低，例如LDMOS晶体管 '）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且具有相同的导电类型延伸至少穿过所述漂移区域（50,50'，90,90'）到所述下部体区域（44,44'，84,84'）中，和/或（ii）将偏压Viso施加到周围的侧向掺杂隔离壁 102）和/或（iii）在隔离壁（102）和漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

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