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21. 发明申请

US20130148406A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US20130148406A1
公开(公告)日：2013-06-13
申请号：US13700329
申请日：2012-07-11
申请人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
发明人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/14 , G11C11/1673 , G11C13/0004 , G11C2013/0054 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/77
摘要： A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
摘要翻译：提供一种能够抑制潜流引起的对存储元件的电阻值的检测灵敏度的降低的交叉点非易失性存储装置。该设备包括垂直位和字线; 交叉点单元阵列，其包括存储单元，每个存储单元具有电阻值，该电阻值根据电信号在至少两个电阻状态之间可逆地改变;布置在字和位线的交叉点上; 偏移检测单元阵列，包括在高电阻状态下具有高于存储单元的电阻的偏移检测单元，所述字线由偏移检测单元阵列共享; 读取电路（读出放大器），其基于通过所选位线的电流确定所选存储单元的电阻状态; 以及在读取操作时段中向偏移检测单元阵列提供电流的电流源。

22. 发明授权

US08154909B2 Resistance variable memory apparatus 有权
标题翻译：电阻变量存储装置
公开(公告)号：US08154909B2
公开(公告)日：2012-04-10
申请号：US13165551
申请日：2011-06-21
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3
摘要翻译：本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL）使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

23. 发明授权

US08982603B2 Cross point variable resistance nonvolatile memory device and method of reading thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US08982603B2
公开(公告)日：2015-03-17
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C11/21 , G11C13/00
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

24. 发明申请

US20130223133A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US20130223133A1
公开(公告)日：2013-08-29
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

25. 发明授权

US08441839B2 Cross point variable resistance nonvolatile memory device 有权
标题翻译：交叉点可变电阻非易失性存储器件
公开(公告)号：US08441839B2
公开(公告)日：2013-05-14
申请号：US13380624
申请日：2011-06-02
申请人： Ryotaro Azuma , Kazuhiko Shimakawa
发明人： Ryotaro Azuma , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , G11C2213/76 , H01L27/0688 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements (57, 58) switch electrical connection and disconnection between a global bit line (56) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit (92) having parallel-connected P-type current limiting element (91) and N-type current limiting element (90) is provided between the global bit line and the switch elements.
摘要翻译：交叉点可变电阻非易失性存储器件包括具有相同取向的存储单元，用于所有层的稳定特性。每个存储单元（51）被放置在X方向上的位线（53）的交叉点的不同的一个和Y层方向上形成的字线（52）。在多路交叉点结构中，共享字线的垂直阵列平面在Y方向上对齐，对于在Z方向上排列的一组位线，偶数和奇数位位线选择开关元件（57,58）切换电连接以及全局位线（56）和共同连接的偶数层位线和共同连接的奇数位位线之间的断开。在全局位线和开关元件之间提供具有并联P型限流元件（91）和N型限流元件（90）的双向限流电路（92）。

26. 发明授权

US08441837B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08441837B2
公开(公告)日：2013-05-14
申请号：US13054312
申请日：2010-04-14
申请人： Yuuichirou Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Yuuichirou Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.
摘要翻译：一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...）第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。

27. 发明授权

US08384061B2 Nonvolatile memory device and manufacturing method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08384061B2
公开(公告)日：2013-02-26
申请号：US12745190
申请日：2008-11-06
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L27/26 , H01L29/8605 , H01L21/02
CPC分类号： H01L27/2409 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).
摘要翻译：本发明的非易失性存储器件包括填充在第一通孔（4）中的基片（1），第一布线（3），第一电阻可变元件（5）和第一二极管元件的下电极（6）分别与第一布线3分别垂直于第一布线3交叉的第二布线（11），每条布线包括第一二极管元件的半导体层（7），导电层（8）和半导体层（ 10）分别被填充到第二通孔（13）中的第二电阻可变元件（16）和第二二极管元件的上电极（14）以及第三电线（17）），并且每个第二布线（11）的导电层（8）也用作第一二极管元件（9）的上电极和第二二极管元件（15）的下电极。

28. 发明申请

US20100172171A1 RESISTANCE VARIABLE MEMORY APPARATUS 有权
标题翻译：电阻可变存储器
公开(公告)号：US20100172171A1
公开(公告)日：2010-07-08
申请号：US12602414
申请日：2008-05-15
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3
摘要翻译：本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL）使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与所选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

29. 发明授权

US09087581B2 Cross point variable resistance nonvolatile memory device and method of writing thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US09087581B2
公开(公告)日：2015-07-21
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

30. 发明授权

US08198618B2 Nonvolatile memory device and manufacturing method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08198618B2
公开(公告)日：2012-06-12
申请号：US12747060
申请日：2008-12-02
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).
摘要翻译：本发明的非易失性存储装置包括基板（1），第一布线（3），分别填充到第一通孔（4）中的第一填充构件（5），分别穿过第一布线 3）分别垂直于第一导线（3），每个第二导线（11）包括多个层，包括第一电阻可变元件中的每一个的电阻变化层（6），导电层（7）和按顺序堆叠在一起的第二电阻可变元件的电阻变化层（8），分别填充到第二通孔（13）中的第二填充组分（14）和第三导线（15），以及导电层第二电线（11）的电极（7）用作第一电阻可变元件（9）的电极和第二电阻可变元件（10）的电极。

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