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21. 发明授权

US07244989B2 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07244989B2
公开(公告)日：2007-07-17
申请号：US11144569
申请日：2005-06-02
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7393 , H01L29/0634 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region. In a particular embodiment, the third semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias applied between the second semiconductor region and the third semiconductor region.
摘要翻译：一种包括绝缘栅双极晶体管（IGBT）（100,200,300,400）的半导体元件和制造方法，包括具有第一导电类型和掩埋半导体区域的半导体衬底（110,210,310,410） 115,215,315,415），其具有位于半导体衬底上方的第二导电类型。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120,220,320,420），具有第一导电类型的第二半导体区域（130,230,330,430）位于第二半导体区域第一半导体区域，具有位于第一半导体区域上方的第二导电类型的第三半导体区域（140,240,340,440），具有设置在第三半导体区域中的第一导电类型的发射极（150,250,350,450）以及设置在第三半导体区域中的具有第一导电类型的集电极（170,270,370,470）。在特定实施例中，第三半导体区域和掩埋半导体区域响应于施加在第二半导体区域和第三半导体区域之间的反向偏压而耗尽第一半导体区域。

22. 发明授权

US07282386B2 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US07282386B2
公开(公告)日：2007-10-16
申请号：US11117996
申请日：2005-04-29
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L21/00
CPC分类号： H01L29/872 , H01L29/063 , H01L29/0692 , H01L29/66136 , H01L29/66143 , H01L29/8611
摘要： A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.
摘要翻译：肖特基器件具有多个单元电池，每个单元电池具有肖特基接触部分，由反向偏置电压条件期间相对于器件的表面在垂直和水平方向上形成耗尽区域的端接结构包围。

23. 发明授权

US06573562B2 Semiconductor component and method of operation 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06573562B2
公开(公告)日：2003-06-03
申请号：US10004186
申请日：2001-10-31
申请人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L2976
CPC分类号： H03K17/08 , H01L21/761 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0676 , H01L27/0814 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.
摘要翻译：半导体元件包括具有第一导电类型的第一和第二部分（111,112）的半导体衬底（110），至少部分地位于半导体衬底中的晶体管（120）和开关电路（150,350,650 ，850）。晶体管包括（i）半导体衬底的第一部分中的第一掺杂区域，并具有第一导电类型（ii）端子，其包括具有第二导电类型并位于半导体的第一部分中的第二掺杂区域衬底并且在第一掺杂区域上方，以及（iii）具有第二导电类型并且位于半导体衬底的第一部分下方并位于半导体衬底的第二部分之下的第三掺杂区域。开关电路电耦合到第三掺杂区域以调节第三掺杂区域的偏置。

24. 发明授权

US06528849B1 Dual-gate resurf superjunction lateral DMOSFET 失效
标题翻译：双栅极复合超导型DMOSFET
公开(公告)号：US06528849B1
公开(公告)日：2003-03-04
申请号：US09652813
申请日：2000-08-31
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2978
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/7393 , H01L29/7831
摘要： A MOSFET includes a source region, a first channel region proximate to the source region, a first gate region adjacent to the first base region, a drain region, a second channel region proximate to the drain region, and a second gate region adjacent to the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate region with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate region with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region includes a set of alternating columns, each of which is also coupled between the first base region and the second base region. The set of alternating columns includes a plurality of columns doped with N− type impurities alternating with a plurality columns doped with P− type impurities.
摘要翻译： MOSFET包括源极区域，靠近源极区域的第一沟道区域，与第一基极区域相邻的第一栅极区域，漏极区域，靠近漏极区域的第二沟道区域以及与漏极区域相邻的第二栅极区域第二通道区域。根据相对于源区域的至少第一部分施加到第一栅极区域的第一电压，在第一沟道区域内形成第一沟道，并且第二沟道形成在第二沟道区内，依赖于相对于漏极区域的至少第二部分施加到第二栅极区域的第二电压。 MOSFET还包括耦合在第一沟道区域和第二沟道区域之间的漂移区域，其中漂移区域包括一组交替的列，其中每一个也耦合在第一基极区域和第二基极区域之间。这组交替的列包括掺杂有多个掺杂有P-型杂质的列的N型杂质的多个列。

25. 发明授权

US07791161B2 Semiconductor devices employing poly-filled trenches 有权
标题翻译：采用多晶填充沟槽的半导体器件
公开(公告)号：US07791161B2
公开(公告)日：2010-09-07
申请号：US11213069
申请日：2005-08-25
申请人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L29/00
CPC分类号： H01L29/0878 , H01L23/3677 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/66681 , H01L29/732 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill. Significant area savings are also achieved.
摘要翻译：为半导体器件提供了结构和方法。这些器件包括填充有高掺杂多晶半导体的沟槽，其从表面延伸到器件的主体中，其中包括：（i）减少衬底电流注入，（ii）降低导通电阻和/或（iii）减少热对基片的阻抗。对于孤立的LDMOS器件，横向隔离壁（连接到源极）和掩埋层之间的电阻降低，从而降低衬底注入电流。当放置在垂直装置的横向装置或收集器的漏极中时，多晶硅填充沟槽有效地放大了漏极或集电极区域，从而降低了导通电阻。对于形成在氧化物隔离层上的器件，多晶填充沟槽期望地穿透该隔离层，从而改善从有源区到衬底的热传导。多孔填充沟槽通过蚀刻和再填充方便地形成。也实现了显着的面积节省。

26. 发明申请

US20090174030A1 LINEARITY CAPACITOR STRUCTURE AND METHOD 有权
标题翻译：线性电容器结构与方法
公开(公告)号：US20090174030A1
公开(公告)日：2009-07-09
申请号：US11969600
申请日：2008-01-04
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L21/283 , H01L29/94
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译：对于MOS电容器（MOS CAP）描述了方法（200）和装置（30,50-53）。装置（30,50-53）包括具有由电介质（35,57,95）覆盖的欧姆耦合的N和P半导体区域（32,34; 54,56; 92,94）的衬底（31）。导电电极（36,58,96）覆盖在这些N和P区域（32,34; 54,56; 92,94）上方的电介质（35,57,95）上。使用欧姆耦合的N和P区域（32,34; 54,56; 92,94）通过与普通MOS CAP相关联的施加电压基本上减小电容的变化（40,64,70,80）。当这些N和P区域（32,34; 54,56; 92,94）具有不同的掺杂时，电容变化（40,64,70,80）仍然可以通过调节电介质的性质（57，（54,56; 92,94）的N区域和/或P区域（54,56; 92,94）或两者的相对区域之间。因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

27. 发明授权

US07329566B2 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07329566B2
公开(公告)日：2008-02-12
申请号：US11142111
申请日：2005-05-31
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L21/332 , H01L21/336
CPC分类号： H01L29/7393 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130). In a particular embodiment, the second semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias potential applied across the semiconductor component.
摘要翻译：一种半导体元件和制造方法，包括绝缘栅双极晶体管（IGBT）（100,200），其包括具有第一导电类型的半导体衬底（110）和具有第二导电类型的掩埋半导体区域（115）半导体衬底。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120），具有位于第一半导体区域的至少一部分上方的第二导电类型的第二半导体区域（130），发射极 150），并且具有设置在第一半导体区域中的具有第二导电类型的集电极（170）。提供沉降片区域（140）以将掩埋的半导体区域（115）电连接到第二半导体区域（130）。在特定实施例中，响应于施加在半导体部件上的反向偏置电位，第二半导体区域和掩埋半导体区域耗尽第一半导体区域。

28. 发明授权

US07095092B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US07095092B2
公开(公告)日：2006-08-22
申请号：US10836170
申请日：2004-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Vijay Parthasarathy
IPC分类号： H01L29/00
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译：在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流进入半导体基板（12）。可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。

29. 发明授权

US07355260B2 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US07355260B2
公开(公告)日：2008-04-08
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译：导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

30. 发明授权

US07180158B2 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07180158B2
公开(公告)日：2007-02-20
申请号：US11144570
申请日：2005-06-02
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L27/082
CPC分类号： H01L29/7393 , H01L29/063 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions (120) having the first conductivity type, a plurality of second semiconductor regions (130) having the first conductivity type, and a plurality of third semiconductor regions (140) having the second conductivity type. A sinker region (142) having the second conductivity type is disposed in a third semiconductor region and a first semiconductor region during manufacture to define the plurality of regions and tie the buried semiconductor region to the plurality of third semiconductor regions. An emitter (150) having the first conductivity type is disposed in one of the third semiconductor regions, a collector (170) having the first conductivity type is disposed in the other of the third semiconductor regions. A field poly plate (162) is provided and tied to the collector (170). In a particular embodiment, the plurality of third semiconductor regions and the buried semiconductor region deplete the plurality of first semiconductor regions in response to a reverse bias potential applied between the plurality of second semiconductor regions and the plurality of third semiconductor regions.
摘要翻译：一种包括具有第一导电类型的半导体衬底（110）和位于半导体衬底上方的具有第二导电类型的掩埋半导体区（115）的绝缘栅双极晶体管（IGBT）（100）的半导体元件和制造方法。 IGBT还包括具有第一导电类型的多个第一半导体区域（120），具有第一导电类型的多个第二半导体区域（130）和具有第二导电类型的多个第三半导体区域（140）。具有第二导电类型的沉降片区域（142）在制造期间设置在第三半导体区域和第一半导体区域中，以限定多个区域并将掩埋半导体区域与多个第三半导体区域相连。具有第一导电类型的发射极（150）设置在第三半导体区域之一中，具有第一导电类型的集电极（170）设置在第三半导体区域中的另一个中。提供了现场多晶板（162）并将其连接到集电器（170）。在特定实施例中，响应于施加在多个第二半导体区域和多个第三半导体区域之间的反向偏置电位，多个第三半导体区域和掩埋半导体区域耗尽多个第一半导体区域。

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