专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070205436A1 Flash memory cell with split gate structure and method for forming the same 有权
标题翻译：具有分离栅结构的闪存单元及其形成方法
公开(公告)号：US20070205436A1
公开(公告)日：2007-09-06
申请号：US11368714
申请日：2006-03-06
申请人： Chen-Ming Huang , Hung-Cheng Sung , Wen-Ting Chu , Chang-Jen Hsieh , Ya-Chen Kao
发明人： Chen-Ming Huang , Hung-Cheng Sung , Wen-Ting Chu , Chang-Jen Hsieh , Ya-Chen Kao
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.
摘要翻译：分离门存储单元。浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。浮栅设置在一对隔离结构之间，并且不与其上表面重叠。盖层设置在浮动栅上。控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。源极区域形成在靠近浮动栅极一侧的衬底中。

22. 发明授权

US07106629B2 Split-gate P-channel flash memory cell with programming by band-to-band hot electron method 有权
标题翻译：分频门P通道闪存单元，采用带对带热电子法进行编程
公开(公告)号：US07106629B2
公开(公告)日：2006-09-12
申请号：US10788949
申请日：2004-02-27
申请人： Wen-Ting Chu , Chia-Ta Hsieh
发明人： Wen-Ting Chu , Chia-Ta Hsieh
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0425 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The split-gate, P-channel structure, which includes a P+ drain, P+ source, floating gate and a control gate, advantageously improves protection from over-erase and hot-hole trap conditions, and improves programming speed and higher injection efficiency. The cell is erased by a polysilicon-polysilicon tunneling technique.
摘要翻译：定义了具有带 - 带热电子（BBHE）编程方法的分裂门P通道快闪存储器单元，以提高电池性能的耐久特性。包括P +漏极，P +源极，浮动栅极和控制栅极的分离栅极P沟道结构有利地提高了对过度擦除和热阱阱条件的保护，并提高了编程速度和更高的注入效率。电池被多晶硅多晶硅隧道技术擦除。

23. 发明申请

US20060170029A1 Novel process for erase improvement in a non-volatile memory device 有权
标题翻译：用于擦除非易失性存储器件中的擦除的新方法
公开(公告)号：US20060170029A1
公开(公告)日：2006-08-03
申请号：US11045850
申请日：2005-01-28
申请人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.
摘要翻译：一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。电介质层被部分蚀刻以形成介电层的多个厚度。去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

24. 发明授权

US07030444B2 Space process to prevent the reverse tunneling in split gate flash 失效
标题翻译：空间过程，以防止分流门闪光中的反向隧道
公开(公告)号：US07030444B2
公开(公告)日：2006-04-18
申请号：US10786798
申请日：2004-02-25
申请人： Kuo-Chi Tu , Wen-Ting Chu , Yi-Shing Chang , Yi-Jiun Lin
发明人： Kuo-Chi Tu , Wen-Ting Chu , Yi-Shing Chang , Yi-Jiun Lin
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.
摘要翻译：公开了一种用于防止反向隧道的分裂门闪存单元结构。在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层，浮栅绝缘体层。栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

25. 发明申请

US20050112828A1 METHOD TO FORM FLASH MEMORY WITH VERY NARROW POLYSILICON SPACING 有权
标题翻译：用非常窄的多晶硅间隔形成闪存的方法
公开(公告)号：US20050112828A1
公开(公告)日：2005-05-26
申请号：US10719722
申请日：2003-11-21
申请人： Wen-Ting Chu , Shih-Chang Liu
发明人： Wen-Ting Chu , Shih-Chang Liu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/76 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.
摘要翻译：实现了在制造集成电路器件中形成晶体管栅极的新方法。该方法包括提供基底。导体层形成在衬底之上，其间具有介电层。形成覆盖在导体层上的掩模层。形成覆盖掩模层的抗蚀剂层。图案化抗蚀剂层，从而选择性地暴露掩模层。抗蚀剂层在抗蚀剂层的边缘之间呈现第一间隔。暴露的掩模层被蚀刻通过，从而选择性地暴露导体层。掩模层的蚀刻边缘是锥形的，使得掩模层在导体层的顶表面处的掩模层边缘之间呈现第二间隔。第二个间距小于第一个间距。蚀刻暴露的导体层从而完成晶体管栅极。

26. 发明授权

US06803625B2 Method with trench source to increase the coupling of source to floating gate in split gate flash 有权
公开(公告)号：US06803625B2
公开(公告)日：2004-10-12
申请号：US10627013
申请日：2003-07-25
申请人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
发明人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
IPC分类号： H01L2978
CPC分类号： H01L27/11521 , H01L27/115
摘要： A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

27. 发明授权

US06787418B2 Method of making the selection gate in a split-gate flash eeprom cell and its structure 失效
标题翻译：在分闸式闪光电池中制作选择栅极的方法及其结构
公开(公告)号：US06787418B2
公开(公告)日：2004-09-07
申请号：US10355134
申请日：2003-01-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

28. 发明授权

US06538277B2 Split-gate flash cell 有权
标题翻译：分离式闪存单元
公开(公告)号：US06538277B2
公开(公告)日：2003-03-25
申请号：US09920601
申请日：2001-08-02
申请人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
发明人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76895 , H01L21/76897 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.
摘要翻译：公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

29. 发明授权

US06534821B2 Structure with protruding source in split-gate flash 有权
公开(公告)号：US06534821B2
公开(公告)日：2003-03-18
申请号：US09927071
申请日：2001-08-10
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

30. 发明授权

US06333228B1 Method to improve the control of bird's beak profile of poly in split gate flash 有权
标题翻译：提高分流闸闪光灯中鸟类喙形状控制的方法
公开(公告)号：US06333228B1
公开(公告)日：2001-12-25
申请号：US09534160
申请日：2000-03-24
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jack Yeh , Wen-Ting Chu , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jack Yeh , Wen-Ting Chu , Di-Son Kuo
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.
摘要翻译：提供了一种方法来改善分裂门闪存单元中聚鸟的鸟嘴形状的控制。在第一实施例中实现鸟嘴形状的控制，其中浮栅的多晶层在高温下退火。退火促进了多晶硅中的小晶粒尺寸和因此更平滑的表面，这又促进了更尖锐的多晶硅尖端。更平滑的多晶面也导致浮栅和控制栅之间的更薄的多晶硅，其与尖锐的多晶硅尖端一起增强了分离栅闪存单元的擦除速度。在第二实施例中，通过为浮置栅极提供非晶硅来进一步提高性能，因为硅的无定形性能产生非常光滑的表面。该光滑表面通过退火转移到硅层的再结晶状态。因此，可以很好地控制鸟的喙。然后，一个尖锐和短的多头尖端来自良好控制和明确定义的鸟的喙。因此，增强的分闸式闪存单元如下。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式