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21. 发明申请

US20120246406A1 EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS 失效
标题翻译：有效的预处理与多个处理器和螺纹
公开(公告)号：US20120246406A1
公开(公告)日：2012-09-27
申请号：US13488215
申请日：2012-06-04
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

22. 发明授权

US06141784A Method and system in a data communications system for the retransmission of only an incorrectly transmitted portion of a data packet 失效
标题翻译：数据通信系统中仅用于重传数据分组的错误发送部分的方法和系统
公开(公告)号：US06141784A
公开(公告)日：2000-10-31
申请号：US979668
申请日：1997-11-26
申请人： Gordon Taylor Davis , Jeffrey Haskell Derby
发明人： Gordon Taylor Davis , Jeffrey Haskell Derby
IPC分类号： G08C25/02 , H04L1/00 , H04L1/16 , H04L1/18
CPC分类号： H04L1/1809 , G08C25/02 , H04L1/1628 , H04L2001/0092
摘要： A method and system in a data processing system are disclosed for the retransmission of only a portion of a data packet which had originally been transmitted incorrectly. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second data link is established between the first and second computer systems, whereby the first and second data links are related. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. Each of the data packets includes a plurality of segments. A determination is made whether each of the plurality of data packets is received correctly. In response to a determination that one of the plurality of data packets is received incorrectly, a portion of the data packet which was transmitted incorrectly is determined. Only the incorrectly transmitted portion of the data packet is then retransmitted by the first computer system utilizing the second data link.
摘要翻译：公开了一种数据处理系统中的方法和系统，用于重传仅原始传输不正确的数据分组的一部分。在第一计算机系统和第二计算机系统之间建立第一数据链路。响应于建立第一数据链路，在第一和第二计算机系统之间建立第二数据链路，由此第一和第二数据链路是相关的。利用第一数据链路将多个数据分组从第一计算机系统发送到第二计算机系统。每个数据分组包括多个分段。确定多个数据分组中的每一个是否被正确地接收。响应于错误地接收到多个数据分组之一的确定，确定了发送不正确的数据分组的一部分。然后，第一计算机系统仅利用第二数据链路重发数据分组的不正确发送的部分。

23. 发明授权

US6049902A Method and system in a data communications system for the establishment of multiple, related data links and the utilization of one data link for recovery of errors detected on another link 失效
标题翻译：用于建立多个相关数据链路的数据通信系统中的方法和系统，以及利用一个数据链路来恢复在另一个链路上检测到的错误
公开(公告)号：US6049902A
公开(公告)日：2000-04-11
申请号：US979044
申请日：1997-11-26
申请人： Gordon Taylor Davis , Jeffrey Haskell Derby
发明人： Gordon Taylor Davis , Jeffrey Haskell Derby
IPC分类号： H04L1/00 , H04L1/18 , G08C25/02 , H03M13/00
CPC分类号： H04L1/1809 , H04L2001/0096
摘要： A method and system in a data communications system are disclosed for the establishment of multiple, related data links and the utilization of one of the data links for error correction of transmission errors occurring on the other data link. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second, related data link is established between the first and second computer systems. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. A determination is made whether each of the plurality of data packets is received correctly. In response to each determination that one of the plurality of data packets is not received correctly, the second computer system transmits a selective rejection packet for the one of the plurality of data packets to the first computer system utilizing the second data link.
摘要翻译：公开了一种数据通信系统中的方法和系统，用于建立多个相关数据链路，以及利用其中一个数据链路来纠错其他数据链路上发生的传输错误。在第一计算机系统和第二计算机系统之间建立第一数据链路。响应于建立第一数据链路，在第一和第二计算机系统之间建立第二相关数据链路。利用第一数据链路将多个数据分组从第一计算机系统发送到第二计算机系统。确定多个数据分组中的每一个是否被正确地接收。响应于所述多个数据分组之一未被正确接收的每个确定，所述第二计算机系统利用所述第二数据链路向所述第一计算机系统发送所述多个数据分组中的所述一个数据分组的选择性拒绝分组。

24. 发明授权

US10534608B2 Local computation logic embedded in a register file to accelerate programs 有权
公开(公告)号：US10534608B2
公开(公告)日：2020-01-14
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/78 , G06F15/16 , G06F9/30 , G06F9/38
摘要： A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

25. 发明申请

US20130152099A1 DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES 有权
公开(公告)号：US20130152099A1
公开(公告)日：2013-06-13
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

26. 发明授权

US5822328A Frame synchronization mechanism for digital simultaneous voice/data modems 失效
标题翻译：数字同步语音/数据调制解调器的帧同步机制
公开(公告)号：US5822328A
公开(公告)日：1998-10-13
申请号：US647537
申请日：1996-05-15
申请人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
发明人： Jeffrey Haskell Derby , Aharon Satt , Uzi Shvadron
IPC分类号： H04J3/06 , H04L7/04 , H04L7/10 , H04M11/06
CPC分类号： H04L7/046 , H04J3/0608 , H04M11/06 , H04L7/10
摘要： A time-division multiplexing synchronization mechanism employs a 1-bit/frame framing channel with a pattern that repeats every 2 frames. Acquisition and reacquisition of synchronization with such a framing pattern is enabled through the use of an explicit synchronization procedure. With this procedure, initial acquisition of frame synchronization as well as reframing after loss of synchronization are carried out while the transmission channel is carrying only a predefined bit pattern. When the receivers are in synchronization, synchronization is monitored and maintained using a 1-bit/frame framing channel, while the communications link is carrying multiplexed bit streams with the appropriate format.
摘要翻译：时分复用同步机制采用具有每2帧重复的模式的1比特/帧成帧信道。通过使用显式的同步过程，可以实现采集和重新获取与这种帧模式的同步。通过该过程，在传输信道仅承载预定义位模式的同时，执行帧同步的初始采集以及丢失同步之后的重构。当接收器处于同步状态时，使用1位/帧成帧通道来监视和维护同步，而通信链路则携带适当格式的多路复用位流。

27. 发明授权

US06519738B1 Method and apparatus for high-speed CRC computation based on state-variable transformation 失效
标题翻译：基于状态变换的高速CRC计算方法和装置
公开(公告)号：US06519738B1
公开(公告)日：2003-02-11
申请号：US09520261
申请日：2000-03-07
申请人： Jeffrey Haskell Derby
发明人： Jeffrey Haskell Derby
IPC分类号： H03M1309
CPC分类号： H03M13/091 , H03M13/616 , H04L1/0041 , H04L1/0061
摘要： A method, and a system for employing the method, for computing a cyclic redundancy code (CRC) of a communication data stream taking a number of bits M at a time to achieve a throughput equaling M times that of a bit-at-a-time CRC computation operating at a same circuit clock speed. The method includes (i) representing a frame of the data stream to be protected as a polynomial input sequence; (ii) determining one or more matrices and vectors relating the polynomial input sequence to a state vector; and (iii) applying a a linear transform matrix for the polynomial input sequence to obtain a transformed version of the state vector. The method can further include (iv) applying a linear transform matrix to the transformed version of the state vector to determine a CRC for the polynomial input sequence, if the communication data stream is received by a network device. The method can further include (v) appending the CRC as a frame check sequence (FCS) to the communication data stream for detection by a receiving device.
摘要翻译：一种用于采用该方法的方法和系统，用于计算一次采用多个比特M的通信数据流的循环冗余码（CRC），以实现等于比特在位的M倍的吞吐量，时间CRC计算以相同的电路时钟速度运行。该方法包括：（i）将待保护的数据流的帧表示为多项式输入序列; （ii）确定将所述多项式输入序列与状态向量相关联的一个或多个矩阵和向量; 以及（iii）对于多项式输入序列应用线性变换矩阵以获得状态向量的变换版本。该方法还可以包括（iv）如果通信数据流被网络设备接收，则将线性变换矩阵应用于状态向量的变换版本以确定多项式输入序列的CRC。该方法还可以包括（v）将CRC作为帧校验序列（FCS）附加到通信数据流以供接收设备检测。

28. 发明授权

US06275583B1 Circuits and methods for improved network interface circuit protection 失效
标题翻译：改善网络接口电路保护的电路和方法
公开(公告)号：US06275583B1
公开(公告)日：2001-08-14
申请号：US09047985
申请日：1998-03-25
申请人： Jeffrey Haskell Derby , David Ross Thomas
发明人： Jeffrey Haskell Derby , David Ross Thomas
IPC分类号： H04M322
CPC分类号： H04M3/22
摘要： A network interface circuit includes an off-hook/on-hook circuit, responsive to the communications network, that provides an off-hook voltage substantially equal to the communications network voltage in an off-hook state and that provides an on-hook voltage in an on-hook state. A voltage controlled current source provides a load current which is proportional to a communications network voltage provided by the communications network. A divider circuit, responsive to the off-hook/on-hook circuit, provides an input voltage and produces an over-voltage, wherein the input voltage is proportional to off-hook or on-hook voltage. A clamping circuit limits the input voltage to one of a first or second predetermined value based on the operating mode and generates a current limited voltage. A control circuit, responsive to the over-voltage and the current-limited voltage and the operating mode and responsive to the off-hook/on-hook circuit, sets the network interface circuit in the off-hook state or the on-hook state based on the input voltage, the current-limited voltage, and the operating mode. Related methods and apparatus are also discussed.
摘要翻译：网络接口电路包括响应于通信网络的摘机/挂机电路，其提供基本上等于摘机状态下的通信网络电压的摘机电压，并且提供挂机电压挂机状态。电压控制电流源提供与由通信网络提供的通信网络电压成比例的负载电流。响应于摘机/挂机电路的分频器电路提供输入电压并产生过电压，其中输入电压与摘机或挂机电压成比例。钳位电路基于操作模式将输入电压限制为第一或第二预定值之一，并产生电流限制电压。响应于过电压和限流电压和操作模式并且响应于摘机/挂机电路的控制电路将网络接口电路设置为摘机状态或挂机状态基于输入电压，限流电压和工作模式。还讨论了相关方法和装置。

29. 发明授权

US09448846B2 Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines 有权
标题翻译：用于将作业调度到多个硬件加速引擎的动态配置的硬件队列
公开(公告)号：US09448846B2
公开(公告)日：2016-09-20
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
摘要翻译：一种具有多个处理资源的计算机系统，包括用于向多个硬件加速器调度和调度处理作业的子系统，所述子系统还包括作业请求器，用于请求具有有限和变化的延迟的作业以在硬件上执行加速器队列控制器，用于管理针对多个硬件加速器的处理作业请求; 以及用于将作业分派到所述多个硬件加速引擎的多个硬件队列，每个队列具有专用的队列入口头部，动态共享具有可配置队列深度限制的队列条目池，以及用于移除所有队列中的一个或多个作业的装置。

30. 发明授权

US06519737B1 Computing the CRC bits at a time for data whose length in bits is not a multiple of M 失效
标题翻译：对于长度不是M倍数的数据，一次计算CRC位
公开(公告)号：US06519737B1
公开(公告)日：2003-02-11
申请号：US09520048
申请日：2000-03-07
申请人： Jeffrey Haskell Derby
发明人： Jeffrey Haskell Derby
IPC分类号： H03M1309
CPC分类号： H03M13/091 , H03M13/616
摘要： A method, and a system for performing the method, for computing cyclic redundancy code (CRC) for use in a communication data stream M bits at a time for an input sequence u(n) whose length is not a multiple of M. The method includes (i) representing a frame of data to be protected as the input sequence; (ii) determining a cyclic redundancy code (CRC) for the input sequence M bits at a time from a state vector, until a last block of the input sequence is reached; (iii) if the last block of the input sequence is full, then determining the CRC to be a completed CRC; and (iv) if the last block of the input sequence is not full, then performing three functions. The method can further include (v) appending the completed CRC as a frame check sequence (FCS) to the communication data stream for detection by a receiving device. The three functions are (a) setting a number of the last bits of the last block equal to zero; (b) processing the last block, padded with the number of last bits equal to zero, according to steps (i) and (ii) to determine a new CRC (yCRC); and (c) running the state vector backwards in time to determine a completed CRC.
摘要翻译：一种方法和用于执行该方法的系统，用于计算在通信数据流中使用的循环冗余码（CRC），用于对于长度不是M的倍数的输入序列u（n），一次M位。该方法包括（i）表示要保护的数据帧作为输入序列; （ii）从状态向量确定输入序列M位的循环冗余码（CRC），直到达到输入序列的最后一个块; （iii）如果输入序列的最后一个块是满的，则确定CRC为完成的CRC; 和（iv）如果输入序列的最后一个块不满，则执行三个功能。该方法还可以包括（v）将完成的CRC作为帧校验序列（FCS）附加到通信数据流以供接收设备检测。这三个功能是（a）将最后一个块的最后一位的数目设置为零; （b）根据步骤（i）和（ii）处理最后一个块的填充数，其最后位数等于零，以确定新的CRC（yCRC）; 和（c）及时地向后运行状态向量以确定完成的CRC。

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