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21. 发明授权

US07582535B2 Method of forming MOS transistor having fully silicided metal gate electrode 有权
标题翻译：形成具有完全硅化金属栅电极的MOS晶体管的方法
公开(公告)号：US07582535B2
公开(公告)日：2009-09-01
申请号：US11158978
申请日：2005-06-22
申请人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
发明人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.
摘要翻译：提供制造具有完全硅化金属栅电极的MOS晶体管的方法。该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。形成了跨越有源区域的绝缘栅极图案。在栅极图案的侧壁上形成间隔物。施加选择性外延生长工艺以在栅极图案上形成半导体层，并且在栅极图案的两侧形成半导体层。在这种情况下，在栅极图案上形成多晶半导体层，同时在栅极图案的两侧的有源区同时形成单晶半导体层。选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。将硅化处理应用于形成栅极减少图案的半导体衬底，以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。

22. 发明授权

US07517750B2 Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same 失效
标题翻译：具有包括金属氧化物层的多层栅极间电介质层的闪存器件及其制造方法
公开(公告)号：US07517750B2
公开(公告)日：2009-04-14
申请号：US11383102
申请日：2006-05-12
申请人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
发明人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.
摘要翻译：本发明的实施例提供了制造存储器件的方法，包括在其上具有有源区的半导体衬底上形成浮置栅极图案，其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层，其中栅极间电介质层通过使用O 3气体作为反应气体在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层，栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极，栅极间电介质层图案和浮置栅极，其中栅极间电介质层图案和控制栅极是顺序堆叠在有源区上，并且在有源区之间形成浮栅，并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

23. 发明授权

US07453962B2 Adaptive frequency control apparatus and method thereof 失效
标题翻译：自适应频率控制装置及其方法
公开(公告)号：US07453962B2
公开(公告)日：2008-11-18
申请号：US10856155
申请日：2004-05-27
申请人： Seung-Hwan Lee , Jin-Up Kim
发明人： Seung-Hwan Lee , Jin-Up Kim
IPC分类号： H04L27/06
CPC分类号： H03J7/04
摘要： The adaptive frequency control apparatus includes: a frequency downstreamer for converting the frequency of the radio frequency signal to a frequency of a defined band according to a reference signal; a frequency error measurer for measuring a frequency error between a frequency of the output signal of the frequency downstreamer and a defined frequency; a loop filter for filtering the frequency error output from the frequency error measurer based on a plurality of operational parameters, the operational parameters being changeable; a differential amplifier for generating a control signal for a voltage control based on the output signal of the loop filter; and a voltage-controlled oscillator for changing the frequency of the reference signal according to the control signal of the differential amplifier.
摘要翻译：自适应频率控制装置包括：频率下行器，用于根据参考信号将射频信号的频率转换成定义频带的频率; 频率误差测量器，用于测量下游频率的输出信号的频率与定义的频率之间的频率误差; 环路滤波器，用于基于多个操作参数对来自频率误差测量器的频率误差进行滤波，所述操作参数是可变的; 差分放大器，用于基于所述环路滤波器的输出信号产生用于电压控制的控制信号; 以及用于根据差分放大器的控制信号改变参考信号的频率的压控振荡器。

24. 发明授权

US07391822B2 Method and apparatus for estimating a sample delay between a transmission signal and a feedback signal in a mobile communication system, and a base station transmitter using the same 失效
标题翻译：用于估计移动通信系统中的发送信号和反馈信号之间的采样延迟的方法和装置以及使用其的基站发射机
公开(公告)号：US07391822B2
公开(公告)日：2008-06-24
申请号：US11126253
申请日：2005-05-11
申请人： Yoo-Seung Song , Jae-Hyok Lee , Seung-Hwan Lee , Ki-Hwan Hwang , Jae-Ho Jeon , Seung-Joo Maeng
发明人： Yoo-Seung Song , Jae-Hyok Lee , Seung-Hwan Lee , Ki-Hwan Hwang , Jae-Ho Jeon , Seung-Joo Maeng
IPC分类号： H04L25/49
CPC分类号： H03F1/3247 , H04B7/2681 , H04B2201/709709 , H04W56/00
摘要： A method and apparatus for estimating a signal delay between a transmission signal which is to be processed in a predetermined communication device of a mobile communication system, and a feedback signal. Each of the transmission and feedback signals is sampled for a predetermined length, and signal power magnitude values are computed in a sample unit and are stored in first and second memory blocks. Mean squared error (MSE) values are computed from a plurality of samples, while a start sample position of one block is shifted on a basis of a start sample position of the other block. A sample delay value is estimated from a start sample position of the one block with a smallest MSE value such that a sample delay between a transmission signal and a feedback signal is closely estimated regardless of a frequency allocation (FA) value.
摘要翻译：一种用于估计在移动通信系统的预定通信设备中要处理的传输信号与反馈信号之间的信号延迟的方法和装置。每个发送和反馈信号被采样预定的长度，并且信号功率幅度值以采样单元计算并存储在第一和第二存储器块中。从多个样本计算均方误差（MSE）值，同时基于另一个块的起始样本位置移位一个块的起始采样位置。从具有最小MSE值的一个块的开始采样位置估计采样延迟值，使得无论频率分配（FA）值如何，传输信号和反馈信号之间的采样延迟被严格估计。

25. 发明申请

US20070087064A1 Composition for preventing and treating climacteric symptoms comprising the extract of sophorae fructus 审中-公开
标题翻译：用于预防和治疗更年期症状的组合物，其包含槐提取物
公开(公告)号：US20070087064A1
公开(公告)日：2007-04-19
申请号：US10580469
申请日：2004-02-09
申请人： Suk-Hyung Kwon , Bo-Sik Hwang , Kuk-Hwan Kim , Seung-Hwan Lee , Eun-Ju Yoon , Seung-Hee Lee , Min-Won Lee , Do-Ik Lee , Yung-Wook Choi , Seong-Soo Joo , Tae-Joon Won , Hee-Chul Kang
发明人： Suk-Hyung Kwon , Bo-Sik Hwang , Kuk-Hwan Kim , Seung-Hwan Lee , Eun-Ju Yoon , Seung-Hee Lee , Min-Won Lee , Do-Ik Lee , Yung-Wook Choi , Seong-Soo Joo , Tae-Joon Won , Hee-Chul Kang
IPC分类号： A61K36/489
CPC分类号： A61K36/489
摘要： The present invention relates to a composition for preventing and treating climacteric symptoms comprising the extract of Sophorae Fructus as an effective ingredient. Precisely, the present invention relates to the extract of Sophorae Fructus having an effect of preventing and treating climacteric symptoms, a composition comprising the extract and a method for preventing and treating climacteric symptoms by administering the composition. The extract of Sophorae Fructus of the present invention has activities of promoting the osteoblast proliferation, inhibiting the secretion of bone-absorptive cytokines, promoting the secretion of growth factors involved in bone-reformation, stimulating the generation of nitric oxide in osteoblasts and inhibiting the osteoclast differentiation. In addition, the extract also reduces the concentration of a bone absorption index and inhibits the decrease of calcium content and bone density. Therefore, the extract of Sophorae Fructus of the present invention can be effectively used for the prevention and the treatment of climacteric symptoms including osteoporosis.
摘要翻译：本发明涉及一种用于预防和治疗更年期症状的组合物，其包含作为有效成分的苦参提取物。正是本发明涉及具有预防和治疗更年期症状的苦参的提取物，包含该提取物的组合物和通过施用该组合物来预防和治疗更年期症状的方法。本发明的苦参提取物具有促进成骨细胞增殖，抑制骨吸收性细胞因子分泌的活性，促进参与骨重建的生长因子的分泌，刺激成骨细胞产生一氧化氮并抑制破骨细胞差异化此外，提取物还降低骨吸收指数的浓度，并抑制钙含量和骨密度的降低。因此，本发明的苦参提取物可以有效地用于预防和治疗包括骨质疏松症的更年期症状。

26. 发明授权

US07135422B2 Methods of forming a multi-layered structure using an atomic layer deposition process and methods of forming a capacitor of an integrated circuit device 有权
标题翻译：使用原子层沉积工艺形成多层结构的方法以及形成集成电路器件的电容器的方法
公开(公告)号：US07135422B2
公开(公告)日：2006-11-14
申请号：US10884507
申请日：2004-07-02
申请人： Gab-Jin Nam , Jong-Wan Kwon , Han-Mei Choi , Jae-Soon Lim , Seung-Hwan Lee , Ki-Chul Kim , Sung-Tae Kim , Young-Sun Kim
发明人： Gab-Jin Nam , Jong-Wan Kwon , Han-Mei Choi , Jae-Soon Lim , Seung-Hwan Lee , Ki-Chul Kim , Sung-Tae Kim , Young-Sun Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/403 , C23C16/405 , C23C16/45529 , H01L21/02175 , H01L21/022 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L28/40 , H01L28/90
摘要： Multi-layered structures formed using atomic-layer deposition processes include multiple metal oxide layers wherein the metal oxide layers are formed without the presence of interlayer oxide layers and may include different metal oxide compositions.
摘要翻译：使用原子层沉积工艺形成的多层结构包括多个金属氧化物层，其中形成金属氧化物层而不存在层间氧化物层，并且可以包括不同的金属氧化物组合物。

27. 发明申请

US20060220106A1 Gate structures of a non-volatile memory device and methods of manufacturing the same 有权
标题翻译：非易失性存储器件的门结构及其制造方法
公开(公告)号：US20060220106A1
公开(公告)日：2006-10-05
申请号：US11375762
申请日：2006-03-15
申请人： Han-Mei Choi , Kyoung-Ryul Yoon , Seung-Hwan Lee , Ki-Yeon Park , Young-Sun Kim
发明人： Han-Mei Choi , Kyoung-Ryul Yoon , Seung-Hwan Lee , Ki-Yeon Park , Young-Sun Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/513
摘要： In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and second material layers including hafnium oxide or zirconium oxide are alternately stacked. A conductive layer is formed on the composite dielectric layer and then a gate structure is formed by patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer.
摘要翻译：在形成非易失性存储器件的栅极结构中，在衬底上形成隧道绝缘层和电荷俘获层。在电荷捕获层上形成复合电介质层，并且具有层叠结构，其中包括氧化铝的第一材料层和包括氧化铪或氧化锆的第二材料层交替堆叠。在复合电介质层上形成导电层，然后通过图案化导电层，复合介电层，电荷俘获层和隧道绝缘层形成栅极结构。

28. 发明申请

US20060175613A1 Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device 失效
标题翻译：外延半导体基板的制造方法及半导体装置的制造方法
公开(公告)号：US20060175613A1
公开(公告)日：2006-08-10
申请号：US11192085
申请日：2005-07-29
申请人： Ho Lee , DongSuk Shin , Tetsuji Ueno , Seung-Hwan Lee , Hwa-Sung Rhee
发明人： Ho Lee , DongSuk Shin , Tetsuji Ueno , Seung-Hwan Lee , Hwa-Sung Rhee
IPC分类号： H01L29/04 , H01L21/36
CPC分类号： H01L21/3221 , H01L21/02529 , H01L21/02532 , H01L21/02535 , H01L21/02573 , H01L21/0262 , H01L27/1463 , H01L27/14643 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.
摘要翻译：在制造外延半导体衬底的方法的示例性实施例中，在半导体衬底上生长吸杂层。然后可以在吸气层上形成外延层，并且可以在外延层上形成半导体器件。

29. 发明申请

US20060038243A1 Transistor and method of manufacturing the same 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：US20060038243A1
公开(公告)日：2006-02-23
申请号：US11071018
申请日：2005-03-03
申请人： Tetsuji Ueno , Dong-Suk Shin , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
发明人： Tetsuji Ueno , Dong-Suk Shin , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/26513 , H01L29/045 , H01L29/165 , H01L29/32 , H01L29/6656 , H01L29/66636 , H01L29/66659
摘要： A transistor of the present invention includes a semiconductor substrate that has a first surface of the {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a side face of the {111} crystal plane connecting the first surface to the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the side face. Impurity regions are formed adjacent to both sides of the gate structure. The impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.
摘要翻译：本发明的晶体管包括半导体衬底，其具有{100}晶面的第一表面，{100}晶面的第二表面的高度低于第一表面的高度，并且 {111}晶面将第一表面连接到第二表面。栅极结构形成在第一表面上。在第二表面和侧面上形成外延层。杂质区域形成在栅极结构的两侧附近。杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

30. 发明申请

US20050170620A1 Transistors for semiconductor device and methods of fabricating the same 有权
标题翻译：用于半导体器件的晶体管及其制造方法
公开(公告)号：US20050170620A1
公开(公告)日：2005-08-04
申请号：US11045060
申请日：2005-01-31
申请人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
发明人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
IPC分类号： H01L21/00 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66537 , H01L29/1083 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.
摘要翻译：本发明公开了一种用于半导体器件的晶体管，其能够防止由于杂质离子的扩散而产生栅极图案中的耗尽电容。本发明还公开了一种制造晶体管的方法。

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