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21. 发明申请

US20110003446A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110003446A1
公开(公告)日：2011-01-06
申请号：US12841719
申请日：2010-07-22
申请人： Erh-Kun Lai , Hang-Ting Lue
发明人： Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/336
CPC分类号： H01L27/0688 , B82Y10/00 , B82Y40/00 , H01L21/8221 , H01L21/84 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66787 , H01L29/66833 , H01L29/775 , H01L29/78696 , H01L29/792
摘要： A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure.
摘要翻译：半导体器件包括绝缘层，沟道结构，绝缘结构和栅极。通道结构包括用于连接两个平台的通道桥。沟道桥的底部与绝缘层隔开一段距离，沟道桥具有多个分离的掺杂区域。绝缘结构围绕通道桥环绕，并且栅极缠绕在绝缘结构周围。

22. 发明授权

US07763927B2 Non-volatile memory device having a nitride-oxide dielectric layer 有权
标题翻译：具有氮化物 - 氧化物电介质层的非易失性存储器件
公开(公告)号：US07763927B2
公开(公告)日：2010-07-27
申请号：US11300813
申请日：2005-12-15
申请人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
发明人： Chao-I Wu , Tzu-Hsuan Hsu , Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L29/513
摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.
摘要翻译：非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

23. 发明申请

US20100148239A1 GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY 有权
标题翻译：半导体器件的门结构和形成字线结构和存储器的方法
公开(公告)号：US20100148239A1
公开(公告)日：2010-06-17
申请号：US12333359
申请日：2008-12-12
申请人： Erh-Kun Lai , Hang-Ting Lue
发明人： Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L29/792 , H01L21/28 , H01L21/768
CPC分类号： H01L27/11568 , H01L21/28282
摘要： A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.
摘要翻译：提供了一种用于半导体器件的栅极结构。栅极结构包括导电结构。绝缘地设置在衬底上的导电结构包括中间部分和两个间隔部分。中间部分具有第一表面和两个第二表面。第一表面位于两个第二表面之间。两个间隔部分分别连接到中间部分的两个第二表面。两个间隔部分的每个的宽度从上到下逐渐增加。

24. 发明授权

US07576386B2 Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer 有权
标题翻译：具有氧化物 - 氧化物 - 氧化物（ONO）顶部介电层的非易失性存储器半导体器件
公开(公告)号：US07576386B2
公开(公告)日：2009-08-18
申请号：US11197668
申请日：2005-08-04
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/94
CPC分类号： H01L29/792 , H01L29/513
摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.
摘要翻译：非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域源极和漏极区域之间的硅衬底。该电池包括形成在衬底的主表面上的底部氧化物层。底部氧化物层设置在靠近阱区域的主表面的一部分上。电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。电介质隧道层包括第一氧化物层，氮化物层和第二氧化物层。擦除NVM单元包括施加正栅极电压以从栅极注入孔。

25. 发明授权

US07560762B2 Asymmetric floating gate NAND flash memory 有权
标题翻译：非对称浮栅NAND闪存
公开(公告)号：US07560762B2
公开(公告)日：2009-07-14
申请号：US11209437
申请日：2005-08-23
申请人： Yen-Hao Shih , Chia-Hua Ho , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Chia-Hua Ho , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/80
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.
摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。因此，浮置栅极下的反相通道可以作为源极/漏极。结果，存储器件不需要浅结或辅助栅。此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

26. 发明授权

US07510924B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07510924B2
公开(公告)日：2009-03-31
申请号：US11836142
申请日：2007-08-09
申请人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
发明人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
IPC分类号： H01L21/337
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/42352
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。跨门位于基板上，跨越垂直翅片结构。载体捕获层位于跨门和基板之间。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

27. 发明授权

US07268379B2 Memory cell and method for manufacturing the same 有权
标题翻译：存储单元及其制造方法
公开(公告)号：US07268379B2
公开(公告)日：2007-09-11
申请号：US11162274
申请日：2005-09-05
申请人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
发明人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
IPC分类号： H01L29/80
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/42352
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。跨门位于基板上，跨越垂直翅片结构。载体捕获层位于跨门和基板之间。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

28. 发明申请

US20060226467A1 P-channel charge trapping memory device with sub-gate 审中-公开
标题翻译：具有子门的P沟道电荷俘获存储器件
公开(公告)号：US20060226467A1
公开(公告)日：2006-10-12
申请号：US11100518
申请日：2005-04-07
申请人： Hang-Ting Lue , Min-Ta Wu , Erh-Kun Lai , Yen-Hao Shih , Chia-Hua Ho , Kuang-Yeu Hsieh
发明人： Hang-Ting Lue , Min-Ta Wu , Erh-Kun Lai , Yen-Hao Shih , Chia-Hua Ho , Kuang-Yeu Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/115 , H01L29/40117 , H01L29/4232 , H01L29/792
摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first inversion region, a second inversion region, and a channel region between the first inversion region and the second inversion region. The semiconductor device further includes a control gate over the channel region and at least one sub-gate over the first and second inversion regions, wherein the control gate does not extend over the at least one sub-gate.
摘要翻译：半导体器件包括半导体衬底。半导体衬底包括第一反转区域，第二反转区域和第一反转区域和第二反转区域之间的沟道区域。所述半导体器件还包括在所述沟道区上的控制栅极以及所述第一和第二反转区域上的至少一个子栅极，其中所述控制栅极不在所述至少一个子栅极上延伸。

29. 发明申请

US20140054535A1 SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
标题翻译：具有改进位线电容的半导体结构
公开(公告)号：US20140054535A1
公开(公告)日：2014-02-27
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

30. 发明授权

US08362615B2 Memory and manufacturing method thereof 有权
公开(公告)号：US08362615B2
公开(公告)日：2013-01-29
申请号：US11892980
申请日：2007-08-29
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578
摘要： A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.

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