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21. 发明申请

US20100039873A1 SENSE AMPLIFIER DRIVING CONTROL CIRCUIT AND METHOD 失效
标题翻译：感应放大器驱动控制电路及方法
公开(公告)号：US20100039873A1
公开(公告)日：2010-02-18
申请号：US12427934
申请日：2009-04-22
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C7/08 , G11C7/1045 , G11C11/4074 , G11C11/4091
摘要： A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device.
摘要翻译：读出放大器驱动控制电路具有稳定的放电特性，通过根据半导体存储器件的组织变化来不同地控制具有驱动电压的节点的放电。读出放大器驱动控制电路包括下拉驱动块，其被配置为提供用于读出放大器的下拉操作的下拉电压，上拉驱动块被配置为顺序地提供用于过驱动的第一电压和用于正常驱动的第二电压作为用于读出放大器的上拉操作的上拉电压，其中第二电压的电压电平低于第一电压的电压电平，以及放电块，其被配置为对具有通过根据半导体存储器件的组织控制放电量来控制第二电压。

22. 发明授权

US07626417B2 On-die-termination control circuit and method 有权
公开(公告)号：US07626417B2
公开(公告)日：2009-12-01
申请号：US12157298
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0292
摘要： On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.

23. 发明申请

US20090153185A1 On-die-termination control circuit and method 失效
标题翻译：片上终端控制电路及方法
公开(公告)号：US20090153185A1
公开(公告)日：2009-06-18
申请号：US12157285
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017
摘要： On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.
摘要翻译：片上终端控制电路包括用于检测掉电模式的模式检测单元和被配置为在断电模式下延迟开/关控制信号的掉电延迟。片上终端控制电路设置有移位寄存器，其被配置为在非掉电模式下与移位时钟同步地延迟导通/截止控制信号，并且在不断电的情况下传送接收无延迟的接通/断开控制信号，断电延迟，被配置为在掉电模式下延迟开/关控制信号，并且不在非掉电模式下延迟开/关控制信号;以及控制器，被配置为控制使能/ 根据由通过移位寄存器的通/断控制信号提供的片上终止操作的使能/禁止定时的信息以及断电延迟来禁止片上终止操作。

24. 发明申请

US20070070781A1 Internal address generator 有权
标题翻译：内部地址发生器
公开(公告)号：US20070070781A1
公开(公告)日：2007-03-29
申请号：US11478083
申请日：2006-06-30
申请人： Seung-Min Oh , Yong-Bok An
发明人： Seung-Min Oh , Yong-Bok An
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C11/4087
摘要： An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.
摘要翻译：内部地址发生器包括多个列地址发生器，模式列地址发生器和驱动时钟发生器。响应于读取驱动时钟，每个列产生器接收对应的地址，附加延迟和CAS延迟以产生内部读取地址，并响应于写入驱动时钟生成内部写入地址。模式列地址生成器接收对应的地址，加法等待时间和CAS等待时间，以响应于带宽读驱动时钟生成模式读地址，并响应于带宽写驱动时钟生成模式写地址。驱动时钟发生器接收附加延迟信号，带宽信号，写使能信号和时钟以产生读驱动时钟，写驱动时钟，带宽读驱动时钟和带宽写驱动时钟。

25. 发明申请

US20070069805A1 Internal voltage generating circuit 失效
标题翻译：内部电压发生电路
公开(公告)号：US20070069805A1
公开(公告)日：2007-03-29
申请号：US11529254
申请日：2006-09-29
申请人： Jun-Gi Choi , Seung-Min Oh
发明人： Jun-Gi Choi , Seung-Min Oh
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.
摘要翻译：内部电压产生电路检测反偏压或抽运电压的电平，并且当检测电压低于参考电压时，基于计数定时的结果来控制振荡信号的周期。内部电压产生电路包括用于检测反向偏压/泵浦电压与参考电压之间的电平差的反向偏置/泵浦电压检测器，用于基于反向偏置的检测结果来控制振荡信号的周期的周期控制器泵浦电压检测器和用于根据振荡信号的激活周期来泵浦反偏压/泵浦电压的泵浦单元。

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