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    • 25. 发明授权
    • Thin oxide mask level defined resistor
    • 薄氧化物掩模级限定电阻
    • US5895960A
    • 1999-04-20
    • US935521
    • 1997-09-23
    • David Marlin FritzYue-Kai LoZhigang MaYehuda Smooha
    • David Marlin FritzYue-Kai LoZhigang MaYehuda Smooha
    • H01L27/08H01L29/8605H01L23/62
    • H01L27/0802H01L29/8605
    • An integrated circuit includes a resistor formed in a doped tub located in a semiconductor substrate. A first highly doped resistor contact region extends outward from the associated contact windows towards a second highly doped resistor contact region. The extent of the underlying tub region that lies between the highly doped tub contact regions largely determines the resistance value. The size and geometry of the highly doped resistor contact regions, and hence the resistance of the resistor, is typically determined by the same mask that defines the thin oxide regions of field effect transistors formed on the IC. In a typical application, the resistor is connected between an output buffer and a bondpad. A multiplicity of output buffers on an IC chip may each connect to corresponding bondpads using a multiplicity of the inventive resistors, which may have the same, or alternatively differing, resistance values. The resistors typically are designed to have identical external dimensions, and so layout of the resistors is facilitated for various types of IC types, including for example application specific integrated circuits (ASICs).
    • 集成电路包括形成在位于半导体衬底中的掺杂桶中的电阻器。 第一高掺杂电阻器接触区域从相关联的接触窗向外延伸到第二高掺杂电阻器接触区域。 位于高掺杂的盆接触区域之间的下面的桶区域的程度在很大程度上决定了电阻值。 高掺杂电阻器接触区域的尺寸和几何形状以及因此电阻器的电阻通常由限定在IC上形成的场效应晶体管的薄氧化物区域的相同掩模来确定。 在典型的应用中,电阻连接在输出缓冲器和接合板之间。 IC芯片上的多个输出缓冲器可以使用多个本发明的电阻器连接到相应的焊盘,其可以具有相同或可选地不同的电阻值。 电阻器通常被设计成具有相同的外部尺寸,因此对于各种类型的IC类型(包括例如专用集成电路(ASIC)),电阻器的布局变得容易。