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21. 发明申请

US20120025343A1 THERMOELECTRIC DEVICE HAVING A VARIABLE CROSS-SECTION CONNECTING STRUCTURE 审中-公开
标题翻译：具有可变交叉部分连接结构的热电装置
公开(公告)号：US20120025343A1
公开(公告)日：2012-02-02
申请号：US13262799
申请日：2009-04-15
申请人： Philip J. Kuekes , Alexandre M. Bratkovski , Hans S. Cho , Nathaniel J. Quitoriano , Theodore I. Kamins , R. Stanley Williams
发明人： Philip J. Kuekes , Alexandre M. Bratkovski , Hans S. Cho , Nathaniel J. Quitoriano , Theodore I. Kamins , R. Stanley Williams
IPC分类号： H01L29/66 , H01L35/34
CPC分类号： H01L35/32
摘要： A thermoelectric device having a variable cross-section connecting structure includes a first electrode, a second electrode, and a connecting structure connecting the first electrode and the second electrode. The connecting structure has a first section and a second section. The width of the second section is greater than the width of the first section, and the width of the first section is less than a width that is approximately equivalent to a phonon mean free path through the first section.
摘要翻译：具有可变横截面连接结构的热电装置包括第一电极，第二电极和连接第一电极和第二电极的连接结构。连接结构具有第一部分和第二部分。第二部分的宽度大于第一部分的宽度，并且第一部分的宽度小于大致等于通过第一部分的声子平均自由程的宽度。

22. 发明授权

US07859054B2 Poly-Si thin film transistor and organic light-emitting display having the same 有权
标题翻译：聚硅薄膜晶体管和有机发光显示器
公开(公告)号：US07859054B2
公开(公告)日：2010-12-28
申请号：US11561572
申请日：2006-11-20
申请人： Huaxiang Yin , Takashi Noguchi , Hyuk Lim , Wenxu Xianyu , Hans S. Cho
发明人： Huaxiang Yin , Takashi Noguchi , Hyuk Lim , Wenxu Xianyu , Hans S. Cho
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/12 , H01L29/78609 , H01L29/78696
摘要： A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.
摘要翻译：薄膜晶体管包括具有非线性电子移动路径的Si基通道，设置在沟道两侧的源极和漏极，设置在沟道上方的栅极，介于通道和栅极之间的绝缘体，以及支撑通道的基板，分别设置在通道的两侧的源极和漏极。

23. 发明申请

US20100200834A1 Crystalline nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same 有权
标题翻译：结晶纳米线基板及其制造方法以及使用其制造薄膜晶体管的方法
公开(公告)号：US20100200834A1
公开(公告)日：2010-08-12
申请号：US12659776
申请日：2010-03-22
申请人： Hans S. Cho , Takashi Noguchi , Wenxu Xianyu , Do-Young Kim , Huaxiang Yin , Xiaoxin Zhang
发明人： Hans S. Cho , Takashi Noguchi , Wenxu Xianyu , Do-Young Kim , Huaxiang Yin , Xiaoxin Zhang
IPC分类号： H01L29/775 , H01L29/04 , H01L29/02 , H01L27/12
CPC分类号： H01L29/0673 , B82Y10/00 , H01L29/0665 , H01L29/66772 , H01L29/78654 , H01L29/78684 , H01L29/78696 , Y10S977/762 , Y10S977/814 , Y10S977/90 , Y10S977/932 , Y10S977/943
摘要： Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
摘要翻译：示例性实施例涉及具有其中可以在基板上形成具有相对较细的线宽的结晶纳米线膜的结构的晶体纳米线基板及其制造方法，以及使用其制造薄膜晶体管的方法。制造结晶纳米线基板的方法可以包括制备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图案化成带状，减小线宽绝缘膜通过底切蚀刻绝缘膜的至少一个侧面，并且通过使硅膜熔化和结晶而在绝缘膜的上表面上形成自对准硅纳米线膜。

24. 发明授权

US07642177B2 Method of manufacturing nanowire 有权
标题翻译：制造纳米线的方法
公开(公告)号：US07642177B2
公开(公告)日：2010-01-05
申请号：US11643706
申请日：2006-12-22
申请人： Hans S. Cho
发明人： Hans S. Cho
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , B82Y10/00 , B82Y30/00 , H01L21/02532 , H01L21/0262 , H01L21/2026 , H01L29/0665 , H01L29/0673 , Y10S977/762
摘要： A method of manufacturing a nanowire, a method of manufacturing a semiconductor apparatus including a nanowire and a semiconductor apparatus formed from the same are provided. The method of manufacturing a semiconductor apparatus may include forming a material layer pattern on a substrate, forming a first insulating layer on the material layer pattern, a first nanowire forming layer and a top insulating layer on the substrate, wherein a total depth of the first insulating layer and the first nanowire forming layer may be formed to be smaller than a depth of the material layer pattern, sequentially polishing the top insulating layer, the first nanowire forming layer and the first insulating layer so that the material layer pattern is exposed, exposing part of the first nanowire forming layer to form an exposed region and forming a single crystalline nanowire on an exposed region of the first nanowire forming layer.
摘要翻译：提供一种纳米线的制造方法，包括纳米线的半导体装置的制造方法以及由该纳米线构成的半导体装置。半导体装置的制造方法可以包括在基板上形成材料层图案，在基板上形成第一绝缘层，在基板上形成第一纳米线形成层和顶部绝缘层，绝缘层和第一纳米线形成层可以形成为小于材料层图案的深度，顺序地抛光顶部绝缘层，第一纳米线形成层和第一绝缘层，使得材料层图案暴露，暴露第一纳米线形成层的一部分以形成暴露区域并在第一纳米线形成层的暴露区域上形成单晶纳米线。

25. 发明授权

US07511381B2 Thin film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07511381B2
公开(公告)日：2009-03-31
申请号：US11248620
申请日：2005-10-13
申请人： Takashi Noguchi , Wenxu Xianyu , Hans S. Cho , Huaxiang Yin
发明人： Takashi Noguchi , Wenxu Xianyu , Hans S. Cho , Huaxiang Yin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/02598 , H01L21/02532 , H01L21/02667 , H01L21/2026 , H01L27/1281 , H01L29/66772
摘要： A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.
摘要翻译：提供薄膜晶体管（TFT）及其制造方法。 TFT包括透明基板，在透明基板的区域上的绝缘层，在绝缘层上包括源极，漏极和沟道区的单晶硅层，以及沟道区上的栅极绝缘膜和栅极电极的单晶硅层。

26. 发明授权

US07390706B2 Method of forming channel region of TFT composed of single crystal Si 有权
标题翻译：形成由单晶硅构成的TFT的沟道区的方法
公开(公告)号：US07390706B2
公开(公告)日：2008-06-24
申请号：US11289312
申请日：2005-11-30
申请人： Hans S. Cho , Takashi Noguchi , Do-young Kim
发明人： Hans S. Cho , Takashi Noguchi , Do-young Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02598 , H01L21/2026 , H01L27/1281 , H01L27/1296 , H01L29/04 , H01L29/66772
摘要： A method of forming a high quality channel region of a TFT by forming a large size monocrystalline silicon thin film using a patterned metal mask and a grain boundary filtering region is provided. The method includes sequentially stacking a first buffer layer and an amorphous silicon layer on a substrate, forming a first silicon region in which crystallization begins, a second silicon region having a width smaller than a width of the first silicon region and located on a central portion of a side of the first silicon region, and a third silicon region having a width than greater the width of the second silicon region and contacting the second silicon region, forming a metal mask partly on the first silicon region, and crystallizing the amorphous silicon layer by cooling the amorphous silicon layer after melting the entire amorphous silicon layer except for a portion of the amorphous silicon layer under the metal mask by radiating laser beams to the patterned amorphous silicon layer.
摘要翻译：提供了通过使用图案化金属掩模和晶界过滤区域形成大尺寸单晶硅薄膜来形成TFT的高质量沟道区域的方法。该方法包括在基板上依次层叠第一缓冲层和非晶硅层，形成开始结晶的第一硅区域，第二硅区域的宽度小于第一硅区域的宽度并位于中心部分并且第三硅区域的宽度大于第二硅区域的宽度并与第二硅区域接触，部分地在第一硅区域上形成金属掩模，并且使非晶硅层结晶通过对图案化的非晶硅层照射激光束，在金属掩模下方的非晶硅层的一部分熔融了整个非晶硅层之后，冷却非晶硅层。

27. 发明申请

US20080118754A1 Single crystal silicon rod fabrication methods and a single crystal silicon rod structure 有权
标题翻译：单晶硅棒制造方法和单晶硅棒结构
公开(公告)号：US20080118754A1
公开(公告)日：2008-05-22
申请号：US11976009
申请日：2007-10-19
申请人： Wenxu Xianyu , Young-soo Park , Hans S. Cho , Huaxiang Yin , Hyuck Lim
发明人： Wenxu Xianyu , Young-soo Park , Hans S. Cho , Huaxiang Yin , Hyuck Lim
IPC分类号： C30B13/06 , B32B9/00
CPC分类号： C30B29/06 , C30B13/24 , C30B25/02 , C30B29/60 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02664 , H01L21/02675 , H01L29/42392 , H01L29/78696 , Y10T428/2962
摘要： A method of fabricating a single crystal silicon rod may include forming an insulation layer on a substrate, forming a hole in the insulation layer, selectively growing silicon in the hole, forming a silicon layer on the hole and on the insulation layer, forming a rod pattern on the silicon layer in a direction that is non-radial with respect to the hole, and melting the silicon layer and crystallizing the silicon layer by illuminating a laser beam on the silicon layer where the rod pattern is formed to generate a nucleation site at a position corresponding to the hole. According to the method, a single crystal silicon rod having no defects may be formed.
摘要翻译：制造单晶硅棒的方法可以包括在衬底上形成绝缘层，在绝缘层中形成孔，选择性地生长孔中的硅，在孔和绝缘层上形成硅层，形成棒在相对于孔的非径向的方向上在硅层上形成图案，并且通过照射形成棒图案的硅层上的激光束来熔化硅层并使硅层结晶，从而在硅层上产生成核位置对应于孔的位置。根据该方法，可以形成没有缺陷的单晶硅棒。

28. 发明申请

US20080038889A1 Fin structure and method of manufacturing fin transistor adopting the fin structure 有权
标题翻译：翅片结构的翅片结构和制造方法
公开(公告)号：US20080038889A1
公开(公告)日：2008-02-14
申请号：US11826420
申请日：2007-07-16
申请人： Hans S. Cho , Young-soo Park , Wenxu Xianyu
发明人： Hans S. Cho , Young-soo Park , Wenxu Xianyu
IPC分类号： H01L21/336 , H01L21/36
CPC分类号： H01L29/66795 , H01L27/105 , H01L27/1052 , H01L29/785
摘要： Provided are a fin structure and a method of manufacturing a fin transistor adopting the fin structure. A plurality of mesa structures including sidewalls are formed on the substrate. A semiconductor layer is formed on the mesa structures. A capping layer is formed on the semiconductor layer. Thus, the semiconductor layer is protected by the capping layer and includes a portion which is to be formed as a fin structure. A portion of an upper portion of the capping layer is removed by planarizing, and thus a portion of the semiconductor layer on upper surfaces of the mesa structures is removed. As a result, fin structures are formed on sides of the mesa structures to be isolated from one another. Therefore, a fin structure having a very narrow width can be formed, and a thickness and a location of the fin structure can be easily controlled.
摘要翻译：提供一种翅片结构和制造采用鳍结构的鳍式晶体管的方法。在基板上形成包括侧壁的多个台面结构。在台面结构上形成半导体层。在半导体层上形成覆盖层。因此，半导体层被覆盖层保护，并且包括将被形成为翅片结构的部分。通过平坦化除去覆盖层的上部的一部分，从而去除台面结构的上表面上的半导体层的一部分。结果，翅片结构形成在台面结构的两侧以彼此隔离。因此，可以形成具有非常窄的宽度的翅片结构，并且可以容易地控制翅片结构的厚度和位置。

29. 发明申请

US20070187668A1 Crystal substrates and methods of fabricating the same 审中-公开
标题翻译：晶体基板及其制造方法
公开(公告)号：US20070187668A1
公开(公告)日：2007-08-16
申请号：US11598040
申请日：2006-11-13
申请人： Takashi Noguchi , Hans S. Cho , Wenxu Xianyu , Huaxiang Yin
发明人： Takashi Noguchi , Hans S. Cho , Wenxu Xianyu , Huaxiang Yin
IPC分类号： H01L31/00 , C30B13/02 , C30B19/00 , H01L29/04
CPC分类号： C30B25/18 , C30B23/025 , H01L21/02381 , H01L21/0242 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/02675 , H01L21/30625
摘要： A single crystal substrate and method of fabricating the same are provided. The single crystal substrate includes an insulator having a window exposing a portion of a substrate, a selective epitaxial growth layer formed on the portion of the substrate exposed through the window and a single crystalline layer formed on the insulator and the selective epitaxial growth layer using the selective epitaxial growth layer as an epitaxial seed layer.
摘要翻译：提供单晶基板及其制造方法。单晶衬底包括具有暴露衬底的一部分的窗口的绝缘体，形成在通过窗口暴露的衬底的部分上的选择性外延生长层和在绝缘体上形成的单晶层和使用所述选择性外延生长层选择性外延生长层作为外延种子层。

30. 发明申请

US20140097398A1 MEMRISTIVE DEVICES AND MEMRISTORS WITH RIBBON-LIKE JUNCTIONS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有类似结点的测量装置和制动器及其制造方法
公开(公告)号：US20140097398A1
公开(公告)日：2014-04-10
申请号：US13881452
申请日：2010-10-29
申请人： Hans S. Cho , Jianhua Yang , Janice H. Nickel
发明人： Hans S. Cho , Jianhua Yang , Janice H. Nickel
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2463 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1683
摘要： Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area.
摘要翻译：公开了用于制造忆阻装置的记忆装置，忆阻器和方法。一方面，忆阻器包括第一电极线和第二电极线。第二电极线和第一电极线限定重叠区域。忆阻器包括与第一电极线接触并设置在第一和第二电极线之间的电极延伸部。在第二电极线和电极延伸部之间设置至少一个结。每个结点接触电极延伸部的一部分并且具有与第二电极线的接点接触面积，并且至少一个结的总和接点面积小于重叠面积。

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