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21. 发明授权

US5153880A Field-programmable redundancy apparatus for memory arrays 失效
标题翻译：用于存储阵列的现场可编程冗余设备
公开(公告)号：US5153880A
公开(公告)日：1992-10-06
申请号：US491749
申请日：1990-03-12
申请人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
发明人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/789 , G11C29/835 , G11C29/838
摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundance apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.
摘要翻译：公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。用户通过具有集成电路半导体存储器阵列的标准电压电平的标准信号路径与冗余设备进行通信。冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。现场可编程冗余装置可以包括诸如EEPROM的非易失性存储装置，以存储具有冗余存储器单元的主存储器单元的替换。在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

22. 发明授权

US5003197A Substrate bias voltage generating and regulating apparatus 失效
标题翻译：基板偏压发生调节装置
公开(公告)号：US5003197A
公开(公告)日：1991-03-26
申请号：US299040
申请日：1989-01-19
申请人： Isao Nojima , Ping Wang , Hung Q. Nguyen
发明人： Isao Nojima , Ping Wang , Hung Q. Nguyen
IPC分类号： G05F3/20 , H03K3/03 , H03K3/354
CPC分类号： G05F3/205 , H03K3/0315 , H03K3/354
摘要： An apparatus for generating and regulating a substrate bias voltage for use in semiconductor devices. The invention comprises a sensor which is responsive to the substrate bias voltage, and generates a continuously variable regulating voltage and a continuously variable oscillator bias voltage. A variable impedance device whose resistance is adjustable over a range of values as a function of said regulating voltage is coupled to a charge pump to control the amount of charge pumped by said charge pump per unit time from the substrate of the semiconductor device. An oscillator whose frequency is continuously controlled by the oscillator bias voltage from the sensor is coupled to said charge pump so as to further control the amount of charge pumped by said charge pump per unit time.
摘要翻译：一种用于产生和调节用于半导体器件的衬底偏置电压的装置。本发明包括响应于衬底偏置电压的传感器，并且产生无级调节电压和连续可变的振荡器偏置电压。一个可变阻抗装置，其电阻在所述调节电压的函数值的范围内是可调节的，耦合到电荷泵，以控制从半导体器件的基板每单位时间泵浦的电荷泵的电荷量。频率由传感器的振荡器偏置电压连续控制的振荡器被耦合到所述电荷泵，以进一步控制每单位时间由所述电荷泵泵浦的电荷量。

23. 发明授权

US06292391B1 Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM 有权
标题翻译：用于控制闪存EEPROM中高电压放电的隔离电路和方法
公开(公告)号：US06292391B1
公开(公告)日：2001-09-18
申请号：US09536387
申请日：2000-03-28
申请人： Isao Nojima
发明人： Isao Nojima
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A high-voltage isolating circuit for controlling the discharge of high-voltage a memory array is provided comprising a line connected to individual memory cells of the memory array, the line having both a high-voltage portion and a low-voltage portion, such that the line is capable of providing a high-voltage and a low-voltage to the memory cells; and an isolation transistor having a first source/drain terminal coupled with the high-voltage portion of the line and an opposing source/drain terminal coupled with the low-voltage portion of the line. Further, the substrate of the transistor is coupled with the high-voltage portion of the line, such that the voltage potential of the line can be maintained within a certain voltage range when the low-voltage portion of the line is at a first voltage potential, and wherein the high-voltage portion of the line can be discharged when the low-voltage portion of the line is at a second voltage potential. As a result, latch-up of the circuit can be prevented.
摘要翻译：提供一种用于控制高电压存储器阵列的放电的高压隔离电路，包括连接到存储器阵列的各个存储单元的线，该线具有高电压部分和低电压部分，使得该线路能够向存储器单元提供高电压和低电压; 以及隔离晶体管，其具有与该线路的高压部分耦合的第一源极/漏极端子和与该线路的低电压部分耦合的相对的源极/漏极端子。此外，晶体管的基板与线的高压部分耦合，使得当线的低电压部分处于第一电压电位时，线的电压电位可以保持在一定电压范围内并且其中当线路的低电压部分处于第二电压电位时，线路的高电压部分可以被放电。结果，可以防止电路的闩锁。

24. 发明授权

US06184668B2 Voltage sensing circuit and method for preventing a low-voltage from being inadvertently sensed as a high-voltage during power-up or power-down 有权
标题翻译：用于防止在上电或掉电期间低电压被无意地感测为高电压的电压感测电路和方法
公开(公告)号：US06184668B2
公开(公告)日：2001-02-06
申请号：US09337569
申请日：1999-06-22
申请人： Isao Nojima , Hung Nguyen
发明人： Isao Nojima , Hung Nguyen
IPC分类号： G05F500
CPC分类号： G11C5/144 , G11C5/143
摘要： A high-voltage sensing circuit is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage during power-up and power-down and triggering a high-voltage operation such as a chip erase. The high-voltage sensing circuit comprises a low-power supply sensing circuit for generating a control signal in response to the detection of a power supply level and a switch, controlled by the control signal, that receives the input voltage and passes an output voltage if the input voltage is greater than a reference voltage. Until the power supply exceeds a certain amount, a switching transistor will be OFF and VIN (the output of the charge pump) will not be high enough. Thus, a low-voltage is prevented from being inadvertently sensed by the high-voltage sensing circuit as a high-voltage and triggering a high-voltage operation such as a chip erase.
摘要翻译：提供了一种高电压感测电路，其抑制或防止在上电和掉电期间低电压被无意地感测为高电压并触发诸如芯片擦除的高电压操作。高电压感测电路包括用于响应于检测到电源电平而产生控制信号的低电源感测电路和由控制信号控制的开关，其接收输入电压并传递输出电压，如果输入电压大于参考电压。直到电源超过一定量，开关晶体管将关闭，VIN（电荷泵的输出）将不会足够高。因此，防止低电压被高电压感测电路无意地感测为高电压并触发诸如芯片擦除的高电压操作。

25. 发明授权

US3950737A Nonvolatile counter circuit 失效
标题翻译：非线性计数器电路
公开(公告)号：US3950737A
公开(公告)日：1976-04-13
申请号：US509490
申请日：1974-09-26
申请人： Yukimasa Uchida , Isao Nojima , Yoshiaki Matsuno
发明人： Yukimasa Uchida , Isao Nojima , Yoshiaki Matsuno
IPC分类号： G11C14/00 , H03K3/356 , H03K5/153 , H03K21/00 , H03K21/02 , H03K21/40 , H03K23/52 , H03K23/54 , G11C11/40 , G11C13/00
CPC分类号： H03K5/153 , H03K21/02 , H03K21/403 , H03K3/356008
摘要： A nonvolatile counter circuit is disclosed which includes a nonvolatile insulated gate type field effect memory transistor interposed between the load and active elements of a flip-flop circuit. A switching element is connected in parallel with the memory transistor and a circuit is provided for returning information stored in the nonvolatile memory transistor to the flip-flop after the circuit power source has been turned on. A circuit is also provided for erasing the information stored in the nonvolatile memory transistor. A circuit element is provided for short-circuiting the switching element, and a circuit is provided for writing the information stored in the flip-flop circuit into the nonvolatile memory transistor at the transient of switching off the power.

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