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21. 发明申请

US20070271450A1 Method and system for enhanced thread synchronization and coordination 审中-公开
标题翻译：增强线程同步和协调的方法和系统
公开(公告)号：US20070271450A1
公开(公告)日：2007-11-22
申请号：US11436292
申请日：2006-05-17
申请人： Kshitij A. Doshi , Quinn A. Jacobson , Anne W. Bracy , Hong Wang
发明人： Kshitij A. Doshi , Quinn A. Jacobson , Anne W. Bracy , Hong Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F12/0815 , G06F2209/523
摘要： Synchronization and communication between concurrent software threads is enhanced. An attempt may be made to acquire a lock associated with a resource. If the lock is not available and/or the attempt fails, a hardware monitor may be configured to detect release of the lock. An asynchronous procedure call responsive to detection of the lock release facilitates another attempt to acquire the lock. Alternatively, upon acquiring the lock a hardware monitor may be configured to detect any attempt to acquire the lock. Access to the protected resource may be maintained until an asynchronous procedure call responsive to the detection of such an attempt. Then state may be restored to a safe point for releasing the lock. Alternatively, processing of reader lock requests may be adapted to a turnstile processing when no writer holds or waits for the lock and then adapted to read-write lock processing whenever a writer requests the lock.
摘要翻译：并发软件线程之间的同步和通信得到增强。可以尝试获取与资源相关联的锁。如果锁不可用和/或尝试失败，则可以配置硬件监视器以检测锁的释放。响应于检测到锁定释放的异步过程调用有助于获取锁的另一尝试。或者，在获取锁定时，可以将硬件监视器配置为检测获取锁的任何尝试。可以保持对受保护资源的访问，直到异步过程调用响应于这种尝试的检测。那么状态可以恢复到一个安全的位置来释放锁。或者，当没有写入器保持或等待锁定时，读取器锁定请求的处理可以适用于十字转门处理，然后每当写入器请求锁定时适合于读写锁定处理。

22. 发明申请

US20170285975A1 TECHNOLOGIES FOR MANAGING IMMUTABLE DATA ON A DATA STORAGE DEVICE 审中-公开
公开(公告)号：US20170285975A1
公开(公告)日：2017-10-05
申请号：US15088955
申请日：2016-04-01
申请人： Sanjeev N. Trika , Kshitij A. Doshi
发明人： Sanjeev N. Trika , Kshitij A. Doshi
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0623 , G06F3/0638 , G06F3/0649 , G06F3/0659 , G06F3/0673 , G06F3/0674 , G06F3/0679
摘要： Technologies for managing immutable data include a data storage device having a data storage controller and memory for storing data. The data storage controller may receive requests from a host of the data storage device to mark data stored in the memory as immutable. In response to the request, the data storage controller is configured to set an immutable flag associated with the identified data to mark the identified data as immutable. The immutable flag, when set, provides an indication that the associated data is unmodifiable. In some embodiments, the data storage device may also compact and/or move the immutable data to an immutable memory region of the memory. Technologies to mark the immutable data as mutable, write to the immutable data, and delete or trim the immutable data are also disclosed.

23. 发明申请

US20170269935A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY 审中-公开
公开(公告)号：US20170269935A1
公开(公告)日：2017-09-21
申请号：US15612204
申请日：2017-06-02
申请人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
发明人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
IPC分类号： G06F9/30 , G06F9/345
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3455
摘要： Instructions and logic provide vector loads and/or stores with stride and mask functionality. In one implementation, a processor is provided that includes decode circuitry to decode an instruction specifying a memory address and a stride length for a set of load operations corresponding to a first plurality of data elements of a destination register. The processor further includes one or more execution units, responsive to the decoded first instruction, to load a first data element from the memory address into a first data element of the destination register, and load a second data element from a memory address that is non-zero multiple of the stride length into a first data element of the destination register.

24. 发明授权

US09747101B2 Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering 有权
公开(公告)号：US09747101B2
公开(公告)日：2017-08-29
申请号：US13977729
申请日：2011-09-26
申请人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Charles R. Yount , Suleyman Sair
发明人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Charles R. Yount , Suleyman Sair
IPC分类号： G06F9/312 , G06F9/30 , G06F15/80 , G06F9/38
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/30145 , G06F9/3836 , G06F15/8061
摘要： Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.

25. 发明授权

US09575757B2 Efficient zero-based decompression 有权
标题翻译：高效的零基减压
公开(公告)号：US09575757B2
公开(公告)日：2017-02-21
申请号：US13991858
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
IPC分类号： G06F9/30 , H03M7/46
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译：一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。第二个掩码基于尾随零的计数。执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。将缓冲区移位并复制到结果，并将源数据元素集合向右移动。如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。

26. 发明申请

US20140025901A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

27. 发明申请

US20140019714A1 VECTOR FREQUENCY EXPAND INSTRUCTION 审中-公开
标题翻译：矢量频率扩展指令
公开(公告)号：US20140019714A1
公开(公告)日：2014-01-16
申请号：US13993068
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles Yount , Bret L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30025 , G06F9/30036 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要翻译：包括硬件解码单元和执行引擎单元的处理器核心。所述硬件解码单元对矢量频率扩展指令进行解码，其中所述向量频率压缩指令包括源操作数和目的操作数，其中所述源操作数指定源向量寄存器，所述源向量寄存器包括一对或多对值和游程长度，根据运行长度将其扩展为该值的运行。执行引擎单元，用于执行解码矢量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及包括在源向量寄存器中运行长度编码的至少一个相同值的运行。

28. 发明授权

US09448794B2 Instruction and logic to provide vector horizontal majority voting functionality 有权
标题翻译：提供向量横向多数投票功能的指令和逻辑
公开(公告)号：US09448794B2
公开(公告)日：2016-09-20
申请号：US13977735
申请日：2011-11-30
申请人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
发明人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
IPC分类号： G06F11/00 , G06F9/30 , G06F11/14 , G06F11/10
CPC分类号： G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
摘要： Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要翻译：指令和逻辑提供向量横向多数投票功能。一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数从源操作数的数据字段数读取的值。

29. 发明申请

US20150293820A1 DISTRIBUTED PERSISTENT MEMORY USING ASYNCHRONOUS STREAMING OF LOG RECORDS 有权
标题翻译：使用日志记录的异步流动分布的记忆
公开(公告)号：US20150293820A1
公开(公告)日：2015-10-15
申请号：US14248913
申请日：2014-04-09
申请人： Kshitij A. Doshi , Rahul Khanna , Minh T. Le
发明人： Kshitij A. Doshi , Rahul Khanna , Minh T. Le
IPC分类号： G06F11/16 , G06F11/14
CPC分类号： G06F17/30578 , G06F3/0619 , G06F3/0644 , G06F3/065 , G06F3/067 , G06F11/1482 , G06F11/203 , G06F11/2048 , G06F11/2097 , G06F17/30368 , G06F2201/84 , G06F2201/855 , G06F2201/87
摘要： Technologies for distributed durable data replication include a computing device having persistent memory that stores a memory state and an update log. The computing device isolates a host partition from a closure partition. The computing device may sequester one or more processor cores for use by the closure partition. The host partition writes transaction records to the update log prior to writing state changes to persistent memory. A replication service asynchronously transmits log records to a remote computing device, which establishes a replica update log in persistent memory. If the host partition fails, the closure partition transmits remaining log records from the update log to the remote computing device. The update log may be quickly replayed when recovering the computing device from failure. The remote computing device may also replay the replica update log to update a remote copy of the state data. Other embodiments are described and claimed.
摘要翻译：用于分布式持久数据复制的技术包括具有存储存储器状态和更新日志的持久存储器的计算设备。计算设备将主机分区与封闭分区隔离开来。计算设备可以隔离一个或多个处理器核以供封闭分区使用。在将状态更改写入持久内存之前，主机分区将事务记录写入更新日志。复制服务将日志记录异步发送到远程计算设备，远程计算设备在持久存储器中建立副本更新日志。如果主机分区失败，则关闭分区将剩余的日志记录从更新日志传输到远程计算设备。从故障恢复计算设备时，可能会快速重播更新日志。远程计算设备还可以重放副本更新日志以更新状态数据的远程副本。描述和要求保护其他实施例。

30. 发明申请

US20140195778A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOAD-OP/STORE-OP WITH STRIDE FUNCTIONALITY 有权
标题翻译：指令和逻辑提供向量负载/存储 - 具有强大的功能
公开(公告)号：US20140195778A1
公开(公告)日：2014-07-10
申请号：US13977728
申请日：2011-09-26
申请人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
发明人： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F9/30185 , G06F9/3455 , G06F9/3808 , G06F9/3877 , G06F9/3887 , G06F15/8061
摘要： Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.
摘要翻译：指令和逻辑提供矢量加载操作和/或存储操作与步幅功能。一些实施例，响应于指令：一组负载，第二操作，目的地寄存器，操作数寄存器，存储器地址和步幅长度; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的跨距长度倍数。第一个掩码值表示元素尚未从内存中加载，第二个值表示元素不需要或已经被加载。对于具有第一个值的每一个，数据元素从存储器加载到相应的目标寄存器位置，并且掩码寄存器中的对应值被改变为第二值。然后使用目的地和操作数寄存器中的相应数据执行第二个操作，以生成结果。指令可能在故障后重新启动。

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