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1. 发明申请

US20070271450A1 Method and system for enhanced thread synchronization and coordination 审中-公开
标题翻译：增强线程同步和协调的方法和系统
公开(公告)号：US20070271450A1
公开(公告)日：2007-11-22
申请号：US11436292
申请日：2006-05-17
申请人： Kshitij A. Doshi , Quinn A. Jacobson , Anne W. Bracy , Hong Wang
发明人： Kshitij A. Doshi , Quinn A. Jacobson , Anne W. Bracy , Hong Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F12/0815 , G06F2209/523
摘要： Synchronization and communication between concurrent software threads is enhanced. An attempt may be made to acquire a lock associated with a resource. If the lock is not available and/or the attempt fails, a hardware monitor may be configured to detect release of the lock. An asynchronous procedure call responsive to detection of the lock release facilitates another attempt to acquire the lock. Alternatively, upon acquiring the lock a hardware monitor may be configured to detect any attempt to acquire the lock. Access to the protected resource may be maintained until an asynchronous procedure call responsive to the detection of such an attempt. Then state may be restored to a safe point for releasing the lock. Alternatively, processing of reader lock requests may be adapted to a turnstile processing when no writer holds or waits for the lock and then adapted to read-write lock processing whenever a writer requests the lock.
摘要翻译：并发软件线程之间的同步和通信得到增强。可以尝试获取与资源相关联的锁。如果锁不可用和/或尝试失败，则可以配置硬件监视器以检测锁的释放。响应于检测到锁定释放的异步过程调用有助于获取锁的另一尝试。或者，在获取锁定时，可以将硬件监视器配置为检测获取锁的任何尝试。可以保持对受保护资源的访问，直到异步过程调用响应于这种尝试的检测。那么状态可以恢复到一个安全的位置来释放锁。或者，当没有写入器保持或等待锁定时，读取器锁定请求的处理可以适用于十字转门处理，然后每当写入器请求锁定时适合于读写锁定处理。

2. 发明授权

US08560781B2 Technique for using memory attributes 有权
标题翻译：使用内存属性的技术
公开(公告)号：US08560781B2
公开(公告)日：2013-10-15
申请号：US13175928
申请日：2011-07-04
申请人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
发明人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：一种使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

3. 发明授权

US07991965B2 Technique for using memory attributes 有权
标题翻译：使用内存属性的技术
公开(公告)号：US07991965B2
公开(公告)日：2011-08-02
申请号：US11349661
申请日：2006-02-07
申请人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
发明人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
IPC分类号： G06F13/376
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

4. 发明申请

US20140025901A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

5. 发明申请

US20110264866A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20110264866A1
公开(公告)日：2011-10-27
申请号：US13175928
申请日：2011-07-04
申请人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
发明人： Quinn A. Jacobson , Anne Weinberger Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham N. Chinya , Bratin Saba , Ali-Reza Adl-Tabatabai , Gad S. Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

6. 发明申请

US20110153529A1 METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTURE MODEL 审中-公开
标题翻译：方法和设备有效地生成处理器架构模型
公开(公告)号：US20110153529A1
公开(公告)日：2011-06-23
申请号：US12646541
申请日：2009-12-23
申请人： Anne W. Bracy , Mahesh Madhav , Hong Wang
发明人： Anne W. Bracy , Mahesh Madhav , Hong Wang
IPC分类号： G06F15/18 , G06N5/02
CPC分类号： G06F17/5022
摘要： A method and apparatus for efficiently generating a processor architecture model that accurately predicts performance of the processor for minimizing simulation time are described. In one embodiment, the method comprises: identifying a performance benchmark of a processor; sampling a portion of a design space for the identified performance benchmark; simulating the sampled portion of the design space to generate training data; generating a processor performance model from the training data by modifying the training data to predict an entire design space; and predicting performance of the processor for the entire design space by executing the processor performance model.
摘要翻译：描述了一种用于有效地生成准确地预测处理器的性能以最小化模拟时间的处理器架构模型的方法和装置。在一个实施例中，该方法包括：识别处理器的性能基准; 对所识别的性能基准的一部分设计空间进行采样; 模拟设计空间的采样部分以产生训练数据; 通过修改训练数据来预测整个设计空间，从训练数据生成处理器性能模型; 并通过执行处理器性能模型来预测处理器对于整个设计空间的性能。

7. 发明申请

US20120084536A1 PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION 有权
标题翻译：提高螺纹水准仪的主要原则
公开(公告)号：US20120084536A1
公开(公告)日：2012-04-05
申请号：US13314826
申请日：2011-12-08
申请人： Quinn A. Jacobson , Hong Wang , John Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan D. Kaushik
发明人： Quinn A. Jacobson , Hong Wang , John Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan D. Kaushik
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
摘要翻译：处理器可以包括地址监视表和原子更新表以支持推测性线程。处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或指令清除与陷阱/异常/中断处理相关联的状态位之一。还描述和要求保护其他实施例。

8. 发明授权

US07610448B2 Obscuring memory access patterns 有权
标题翻译：模糊内存访问模式
公开(公告)号：US07610448B2
公开(公告)日：2009-10-27
申请号：US11646642
申请日：2006-12-27
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/14 , G06F11/00 , G06F12/16 , G06F15/18 , G08B23/00
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

9. 发明申请

US20100299479A1 OBSCURING MEMORY ACCESS PATTERNS 有权
标题翻译：记忆存取模式
公开(公告)号：US20100299479A1
公开(公告)日：2010-11-25
申请号：US12562041
申请日：2009-09-17
申请人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
发明人： Mark Buxton , Ernie Brickell , Quinn A. Jacobson , Hong Wang , Baiju Patel
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/30047 , G06F12/1458 , G06F21/52 , G06F21/78
摘要： For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.
摘要翻译：对于与线程相关联的一组存储器位置中的每个存储器位置，设置与存储器位置相关联的指示，以便如果来自存储器位置的数据被从高速缓存中移出，则请求信号; 并且响应于该信号，将该组存储器位置重新加载到高速缓存中。

10. 发明申请

US20130073835A1 PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION 审中-公开
标题翻译：提高螺纹水准仪的主要原则
公开(公告)号：US20130073835A1
公开(公告)日：2013-03-21
申请号：US13675910
申请日：2012-11-13
申请人： Quinn A. Jacobson , Hong Wang , John P. Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant E. Bigbee , Shivnandan D. Kaushik
发明人： Quinn A. Jacobson , Hong Wang , John P. Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant E. Bigbee , Shivnandan D. Kaushik
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
摘要翻译：处理器可以包括地址监视表和原子更新表以支持推测性线程。处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或指令清除与陷阱/异常/中断处理相关联的状态位之一。还描述和要求保护其他实施例。

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