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21. 发明申请

US20110235386A1 Semiconductor Memory Device and Manufacturing Method of the Same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110235386A1
公开(公告)日：2011-09-29
申请号：US13154113
申请日：2011-06-06
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C5/02
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

22. 发明申请

US20070228455A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070228455A1
公开(公告)日：2007-10-04
申请号：US11619561
申请日：2007-01-03
申请人： Yoshitaka Sasago , Tomoyuki Ishii , Toshiyuki Mine
发明人： Yoshitaka Sasago , Tomoyuki Ishii , Toshiyuki Mine
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： In the memory array area of a semiconductor substrate, memory cells of a NAND flash memory are arranged in a matrix in the row direction and the column direction. A plurality of memory cells arranged in the row direction are mutually isolated by device isolation trenches having a thin strip planar shape extending in the column direction. The diameter of the device isolation trenches in the row direction at the bottom portion thereof is larger than that near the surface.
摘要翻译：在半导体衬底的存储器阵列区域中，NAND闪速存储器的存储单元被排列成行方向和列方向的矩阵。沿行方向布置的多个存储单元通过在列方向上延伸的薄的带状平面形状的器件隔离沟相互隔离。器件隔离沟槽在其底部的行方向上的直径大于靠近表面的直径。

23. 发明申请

US20110169070A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110169070A1
公开(公告)日：2011-07-14
申请号：US13072211
申请日：2011-03-25
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L27/088
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

24. 发明授权

US07309892B2 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US07309892B2
公开(公告)日：2007-12-18
申请号：US11439152
申请日：2006-05-24
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

25. 发明授权

US07061053B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US07061053B2
公开(公告)日：2006-06-13
申请号：US10929424
申请日：2004-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

26. 发明授权

US07009243B2 Semiconductor memory device 失效
公开(公告)号：US07009243B2
公开(公告)日：2006-03-07
申请号：US10985946
申请日：2004-11-12
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L29/788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

27. 发明申请

US20050087797A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050087797A1
公开(公告)日：2005-04-28
申请号：US10985946
申请日：2004-11-12
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L27/10 , B82B1/00 , G11C11/404 , G11C11/405 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L27/115 , H01L29/788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.
摘要翻译：半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一渠道区域第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端的第一晶体管连接到数据线。

28. 发明授权

US06646300B2 Semiconductor memory device 失效
公开(公告)号：US06646300B2
公开(公告)日：2003-11-11
申请号：US09811555
申请日：2001-03-20
申请人： Tomoyuki Ishii , Kazuo Yano
发明人： Tomoyuki Ishii , Kazuo Yano
IPC分类号： H01L29788
CPC分类号： G11C11/405 , G11C11/404 , H01L27/0688 , H01L27/115 , H01L27/11551 , H01L27/1156
摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

29. 发明申请

US20080042193A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080042193A1
公开(公告)日：2008-02-21
申请号：US11896800
申请日：2007-09-06
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

30. 发明申请

US20050237786A1 Semiconductor memories 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20050237786A1
公开(公告)日：2005-10-27
申请号：US11155780
申请日：2005-06-20
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： G11C11/00 , G11C11/401 , G11C11/405 , G11C11/406 , G11C11/4076 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/12
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译：本发明提供了高集成度的动态随机存取存储器。此外，提供了一种写入方法，使得减小了二晶体管和三晶体管增益单元存储器的单元尺寸。一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。通过本发明也实现了具有低操作功率和高密度的动态存储单元。

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