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21. 发明授权

US06790742B2 Chemical mechanical polishing in forming semiconductor device 有权
标题翻译：化学机械抛光成型半导体器件
公开(公告)号：US06790742B2
公开(公告)日：2004-09-14
申请号：US10293243
申请日：2002-11-13
申请人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
发明人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。该方法包括以下步骤。形成衬底上的氮化硅层。在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。去除每个大活性区域的氧化物层和对准标记。去除部分反向主动掩模。氧化层平坦化。

22. 发明授权

US06743721B2 Method and system for making cobalt silicide 失效
标题翻译：制造硅化钴的方法和系统
公开(公告)号：US06743721B2
公开(公告)日：2004-06-01
申请号：US10166307
申请日：2002-06-10
申请人： Water Lur , David Lee , Kuang-Chih Wang
发明人： Water Lur , David Lee , Kuang-Chih Wang
IPC分类号： H01L2144
CPC分类号： H01L21/67167 , H01L21/28052 , H01L21/28518 , H01L21/67184 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.
摘要翻译：公开了一种用于制造硅化钴材料的簇工具和许多不同的工艺。 Co-Ti合金层与Co层的组合进行排列并进行热处理，以实现硅化物反应。所得到的结构具有极低的电阻，并且显示出很小的线宽依赖性，因此使它们对于用于半导体处理特别有吸引力。集群工具配置有适当的溅射靶/热组件以实现硅化物反应的许多所需操作，从而导致更高的节省量，生产率等。

23. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

24. 发明授权

US6100205A Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process 失效
标题翻译：使用高密度等离子体化学气相沉积工艺，具有低介电常数的金属间介电层形成
公开(公告)号：US6100205A
公开(公告)日：2000-08-08
申请号：US958828
申请日：1997-10-28
申请人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
IPC分类号： C23C16/04 , C23C16/40 , C23C16/50 , H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , C23C16/50 , H01L21/022 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76801
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积介电层。执行第一HDPCVD步骤以在布线上形成布线之间的间隙中的第一介电层。执行PECVD步骤以将电介质材料沉积在第一介电层上并且在间隙内并限定开口。执行第二HDPCVD步骤，并且由PECVD步骤限定的开口被第三介电层覆盖。该方法允许以相当可控的方式在相邻的金属布线之间形成空气填充的空隙，这允许选择空隙的形状和空隙的顶部的精确定位。此外，空隙通过比典型的更致密和更耐用的材料密封。

25. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

26. 发明授权

US6024106A Post-CMP wafer clean process 有权
标题翻译： CMP后晶圆清洁工艺
公开(公告)号：US6024106A
公开(公告)日：2000-02-15
申请号：US195794
申请日：1998-11-19
申请人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
发明人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
IPC分类号： B08B3/12 , C11D7/26 , C11D7/32 , C11D11/00 , H01L21/00 , B08B6/00 , C11D9/04
CPC分类号： H01L21/67057 , B08B3/12 , C11D11/0047 , C11D11/007 , C11D7/3218
摘要： A post-CMP wafer clean process. A post-CMP wafer is provided. A portion of particles and slurry are removed from the wafer by double side scrubber. The residual particles and slurry are then removed from the wafer in a solvent tank by magasonic and a solvent in the solvent tank includes an amine-based compound.
摘要翻译：后CMP晶圆清洁工艺。提供了后CMP晶片。通过双面洗涤器将一部分颗粒和浆料从晶片上除去。然后通过磁共振在溶剂罐中从晶片上除去残留的颗粒和浆料，溶剂槽中的溶剂包括胺类化合物。

27. 发明授权

US6020258A Method for unlanded via etching using etch stop 失效
标题翻译：使用蚀刻停止法进行无衬底通孔蚀刻的方法
公开(公告)号：US6020258A
公开(公告)日：2000-02-01
申请号：US982266
申请日：1997-12-01
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76834 , Y10S438/97
摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
摘要翻译：形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。在层间电介质的表面上设置一级布线。第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

28. 发明授权

US6017817A Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US6017817A
公开(公告)日：2000-01-25
申请号：US309186
申请日：1999-05-10
申请人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
发明人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76807
摘要： A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
摘要翻译：一种制造双镶嵌结构的方法。在具有有源区的基板上依次形成低k电介质层和盖层。在盖层上形成第一光致抗蚀剂层，然后对盖层进行图案化以暴露低k电介质层的一部分。同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。当执行去除第二光致抗蚀剂层的步骤时，形成通孔，以通过同时去除暴露的低k电介质层来暴露有源区。通孔和布线开口填充有金属层以形成布线和通孔。

29. 发明授权

US06017790A Method of manufacturing embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的制作方法
公开(公告)号：US06017790A
公开(公告)日：2000-01-25
申请号：US173706
申请日：1998-10-15
申请人： Fu-Tai Liou , Water Lur
发明人： Fu-Tai Liou , Water Lur
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10852
摘要： A method of manufacturing embedded DRAM capable of integrating memory circuit regions and logic circuit regions together such that their top surfaces are at the same height, and hence able to maintain a high degree of planarity in integrated circuits. The method includes depositing a layer of refractory metal oxide over a high aspect ratio contact hole. Then, through the selective application of a hydrogen plasma treatment or hot hydrogen treatment, a portion of the deposited refractory metal oxide on the contact hole is transformed from non-conductive to conductive material, whereas the refractory metal oxide without a hydrogen plasma treatment or hot hydrogen treatment remains non-conductive. Therefore, a non-conductive refractory metal oxide layer can be used as a dielectric layer for a DRAM capacitor.
摘要翻译：一种制造嵌入式DRAM的方法，其能够将存储器电路区域和逻辑电路区域集成在一起，使得它们的顶表面处于相同的高度，因此能够在集成电路中保持高度的平面度。该方法包括在高纵横比接触孔上沉积难熔金属氧化物层。然后，通过选择性地施加氢等离子体处理或热氢处理，将接触孔上沉积的难熔金属氧化物的一部分从非导电材料转变为导电材料，而不进行氢等离子体处理或热处理的难熔金属氧化物氢气处理保持不导通。因此，可以使用非导电难熔金属氧化物层作为DRAM电容器的介质层。

30. 发明授权

US5968610A Multi-step high density plasma chemical vapor deposition process 失效
标题翻译：多级高密度等离子体化学气相沉积工艺
公开(公告)号：US5968610A
公开(公告)日：1999-10-19
申请号：US959407
申请日：1997-10-28
申请人： Chih-Chien Liu , Kuen-Jian Chen , Yu-Hao Chen , J. Y. Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Kuen-Jian Chen , Yu-Hao Chen , J. Y. Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/316 , H01L21/762 , B05D3/06 , H01L21/76
CPC分类号： H01L21/02112 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76224
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积三个氧化物层。进行第一HDPCVD步骤，同时保持衬底不偏差以在线和间隙中形成氧化物层。衬底被偏置的第二HDPCVD步骤在第一氧化物层上沉积第二氧化物层。在第二HDPCVD步骤期间，发生一些蚀刻，并且去除第一氧化物层的一部分。以比用第二步骤更大的蚀刻和溅射速率进行第三HDPCVD步骤，以完成用电介质材料填充间隙。第一氧化物层用于在第三步骤期间保护下面的结构免受蚀刻损伤。布线之间的间隙可以填充介电材料，而不会形成空隙，即使对于高纵横比的间隙也是如此。

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