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21. 发明授权

US06930915B2 Cross-point MRAM array with reduced voltage drop across MTJ's 失效
标题翻译：跨点MRAM阵列，MTJ的电压降降低
公开(公告)号：US06930915B2
公开(公告)日：2005-08-16
申请号：US10465003
申请日：2003-06-19
申请人： Stefan Lammers , Hans-Heinrich Viehmann , John Kenneth DeBrosse
发明人： Stefan Lammers , Hans-Heinrich Viehmann , John Kenneth DeBrosse
IPC分类号： G11C11/15 , G11C11/14
CPC分类号： G11C11/15
摘要： A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.
摘要翻译：一种在交叉点磁存储器阵列和交叉点磁存储器件结构中存储信息的方法。在写入操作期间，跨越磁隧道结（MTJ）的电压降最小化，以防止损坏阵列的MTJ。选择的MTJ，未选择的MTJ或两者的电压降在写操作期间被最小化，减少了MTJ的压力，减少了泄漏电流，降低了功耗并增加了写入裕度。

22. 发明申请

US20050078531A1 Reference current distribution in MRAM devices 失效
标题翻译： MRAM器件中的参考电流分布
公开(公告)号：US20050078531A1
公开(公告)日：2005-04-14
申请号：US10683965
申请日：2003-10-10
申请人： Stefan Lammers
发明人： Stefan Lammers
IPC分类号： G11C11/16 , G11C11/15
CPC分类号： G11C11/16
摘要： A reference current distribution method and structure thereof for MRAM devices. An MRAM array includes current reference paths with substantially uniform length and resistance for all current paths flowing from the global reference current generator (GRCG) to a plurality of local current generators (LCGs), each LCG being coupled to at least one sub-array. The conductive wire segments that couple the LCGs to the GRCG are positioned such that all reference current path lengths from the GRCG to each LCG are substantially the same, ensuring that the resistance of all reference current paths is substantially the same and the amount of reference current provided by the GRCG to the LCGs is substantially the same. An advantage of an embodiment of present invention may be that the write margin is increased for the MRAM chip.
摘要翻译： MRAM器件的参考电流分布方法及其结构。 MRAM阵列包括对于从全局参考电流发生器（GRCG）流向多个局部电流发生器（LCG）的所有电流路径具有基本均匀的长度和电阻的电流参考路径，每个LCG耦合到至少一个子阵列。将LCG耦合到GRCG的导线段被定位成使得从GRCG到每个LCG的所有参考电流路径长度基本相同，确保所有参考电流路径的电阻基本相同，并且参考电流量由GRCG提供给LCGs基本相同。本发明的一个实施例的优点可以在于MRAM芯片的写入裕度增加。

23. 发明授权

US06853229B2 Circuit for transforming a single ended signal into a differential mode signal 失效
标题翻译：用于将单端信号变换为差模信号的电路
公开(公告)号：US06853229B2
公开(公告)日：2005-02-08
申请号：US10391850
申请日：2003-03-19
申请人： Hans-Heinrich Viehmann , Stefan Lammers
发明人： Hans-Heinrich Viehmann , Stefan Lammers
IPC分类号： H03K3/037 , H03K5/151 , H03K3/356
CPC分类号： H03K5/151 , H03K3/0375
摘要： An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter 505) and a pair of latches (for example, latches 510 and 520). One latch has as its input an input signal to be converted and the other latch has as its input an inverse of the input signal. The latches maybe clocked by a differential mode clock and remove a timing mismatch between the input signal and its inverse that is incurred via the inverter. The latch outputs are then provided to a differential mode buffer to perform signal voltage and current compatibility transformations.
摘要翻译：一种用于将单端信号变换为差模信号的装置。优选实施例包括逆变器（例如，反相器505）和一对锁存器（例如，锁存器510和520）。一个锁存器具有作为其输入的输入信号，并且另一个锁存器具有作为输入信号的反相的输入信号。锁存器可以由差分模式时钟计时，并消除通过变频器产生的输入信号与其反相之间的定时失配。然后将锁存器输出提供给差分模式缓冲器，以执行信号电压和电流兼容性转换。

24. 发明授权

US06825707B2 Current mode logic (CML) circuit concept for a variable delay element 有权
标题翻译：可变延迟元件的电流模式逻辑（CML）电路概念
公开(公告)号：US06825707B2
公开(公告)日：2004-11-30
申请号：US10384860
申请日：2003-03-10
申请人： Hans-Heinrich Viehmann , Stefan Lammers
发明人： Hans-Heinrich Viehmann , Stefan Lammers
IPC分类号： H03K1762
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/00156 , H03K2005/00208
摘要： An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.
摘要翻译：一种用于电流模式逻辑可变延迟元件的装置。优选实施例包括提供给缓冲（经由缓冲器（例如，缓冲器205））和非缓冲形式的多路复用器（例如，多路复用器210）的输入信号。可以使用多路复用器的控制信号来从缓冲或非缓冲输入信号中进行选择。通过使用中间值（选择缓冲或非缓冲输入信号的值之间的某处）的控制信号，多路复用器然后可以将缓冲和非缓冲输入信号与控制信号的值成比例地组合，并且在可能在由缓冲器赋予的延迟之间的输入信号。

25. 发明授权

US06781896B2 MRAM semiconductor memory configuration with redundant cell arrays 失效
标题翻译：具有冗余单元阵列的MRAM半导体存储器配置
公开(公告)号：US06781896B2
公开(公告)日：2004-08-24
申请号：US10135416
申请日：2002-04-30
申请人： Stefan Lammers , Dietmar Gogl , Gerhard Müller
发明人： Stefan Lammers , Dietmar Gogl , Gerhard Müller
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.
摘要翻译： MRAM半导体存储器配置具有交叉点阵列或晶体管阵列形式的MRAM主单元阵列以及布置在多个平面中并设置在同一芯片上的冗余MRAM存储单元形成的冗余MRAM单元阵列。冗余MRAM单元阵列分布在存储器矩阵的各个平面上，或者整体使用存储器阵列的一个平面来提供冗余单元阵列。

26. 发明授权

US06744662B2 Magnetoresistive memory (MRAM) 失效
标题翻译：磁阻记忆体（MRAM）
公开(公告)号：US06744662B2
公开(公告)日：2004-06-01
申请号：US10436428
申请日：2003-05-12
申请人： Martin Freitag , Dietmar Gogl , Heinz Hoenigschmid , Stefan Lammers
发明人： Martin Freitag , Dietmar Gogl , Heinz Hoenigschmid , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16
摘要： The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.
摘要翻译：多个磁存储器单元的单元阵列的引线的形式通过偏离引线的正方形横截面而被优化，使得位于单元阵列平面中的写入电流的磁场分量充分快速地减小，增加距离交叉点的距离。单元阵列由列引线和行引线的矩阵构成。

27. 发明授权

US06594191B2 Segmented write line architecture 失效
标题翻译：分段写行架构
公开(公告)号：US06594191B2
公开(公告)日：2003-07-15
申请号：US10016859
申请日：2001-12-13
申请人： Stefan Lammers , Christian Arndt
发明人： Stefan Lammers , Christian Arndt
IPC分类号： G11C700
CPC分类号： G11C11/16
摘要： This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a selected segment get a high hard axis field generated by a write line current. Memory cells of deselected segments do not receive this hard axis field. This prevents an undesired state change in particularly sensitive memory cells.
摘要翻译：本发明提出了一种用于写磁层随机存取存储器（MRAM）的新型写入线分割架构。只有所选段中的存储单元才能获得由写入线电流产生的高硬轴字段。取消选择的段的存储单元不接收该硬轴字段。这防止在特别敏感的存储器单元中的不期望的状态改变。

28. 发明授权

US06539506B1 Read/write memory with self-test device and associated test method 有权
标题翻译：使用自检装置读取/写入存储器和相关的测试方法
公开(公告)号：US06539506B1
公开(公告)日：2003-03-25
申请号：US09431529
申请日：1999-11-01
申请人： Stefan Lammers , Werner Weber
发明人： Stefan Lammers , Werner Weber
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G11C29/44
摘要： A read/write memory includes a monolithically integrated self-test device which iteratively enables a defect test with a redundancy analysis, without significant external test aids. The test is achieved essentially by virtue of the fact that word lines to be repaired are stored and excluded from further examinations and in each case the line having the most defects not previously detected is always determined and examined first, until either the number of repair lines no longer suffices or no more defects occur. An associated test method is also provided.
摘要翻译：读/写存储器包括一个单片集成的自检设备，它可以通过冗余分析迭代地启用缺陷测试，而无需大量的外部测试帮助。测试基本上是由于要修复的字线被存储并排除在进一步检查之外，并且在每种情况下，首先确定和检查具有最初缺陷的线，直到修复线的数目不再足够或没有更多的缺陷发生。还提供了相关的测试方法。

29. 发明授权

US06459631B2 Configuration for implementing redundancy for a memory chip 有权
公开(公告)号：US06459631B2
公开(公告)日：2002-10-01
申请号：US09907783
申请日：2001-07-18
申请人： Helmut Fischer , Helmut Kandolf , Stefan Lammers
发明人： Helmut Fischer , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/812 , G11C29/844
摘要： The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.

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