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1. 发明授权

US08953294B2 Circuit arrangement with an overcurrent fuse 有权
标题翻译：具有过流保险丝的电路布置
公开(公告)号：US08953294B2
公开(公告)日：2015-02-10
申请号：US12326590
申请日：2008-12-02
申请人： Alfons Graf , Christian Arndt
发明人： Alfons Graf , Christian Arndt
IPC分类号： H02H3/08 , H02H9/02 , H03K17/082 , H02H3/00 , H02H7/00 , H02H9/08 , H02H3/22 , H03K17/08
CPC分类号： H03K17/0822 , H03K2017/0806
摘要： A circuit arrangement includes a semiconductor switch having a control terminal and a load path. A drive circuit is coupled to the control terminal of the semiconductor switch. The drive circuit has a current measuring arrangement for determining a load current flowing through the load path and is designed to prevent the semiconductor switch from being driven in the off state if the load current exceeds a predetermined load current threshold value. A fuse is coupled in series with the load path of the semiconductor switch triggers if a triggering condition dependent at least on the load current is present.
摘要翻译：电路装置包括具有控制端和负载路径的半导体开关。驱动电路耦合到半导体开关的控制端子。驱动电路具有用于确定流过负载路径的负载电流的电流测量装置，并被设计成如果负载电流超过预定的负载电流阈值，则防止半导体开关被驱动为断开状态。如果存在至少依赖于负载电流的触发条件，则熔丝与半导体开关的负载路径串联耦合。

2. 发明申请

US20120176164A1 Circuit Arrangement Having a Load Transistor and a Voltage Limiting Circuit and Method for Driving a Load Transistor 有权
标题翻译：具有负载晶体管和限压电路的电路布置及驱动负载晶体管的方法
公开(公告)号：US20120176164A1
公开(公告)日：2012-07-12
申请号：US13423121
申请日：2012-03-16
申请人： Christian Arndt , Veli Kartal , Rainald Sander
发明人： Christian Arndt , Veli Kartal , Rainald Sander
IPC分类号： H03K3/00
CPC分类号： H03K17/0822 , H01L23/62 , H01L24/48 , H01L27/0255 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/12035 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection, a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal, a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor, a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.
摘要翻译：本发明涉及具有以下特征的电路装置：具有控制连接和第一和第二负载连接的负载晶体管，耦合到负载晶体管的控制连接并用于施加驱动信号的驱动连接，连接在负载连接中的一个和晶体管的驱动连接之间的电压限制电路，连接到电压限制电路并且以取决于去激活信号的方式停用电压限制电路的去激活电路，该停用电路是依赖的通过负载晶体管的负载电流和/或负载晶体管的驱动电压。

3. 发明申请

US20050088216A1 Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor 审中-公开
标题翻译：具有负载晶体管的电路装置和用于驱动负载晶体管的电压限制电路和方法
公开(公告)号：US20050088216A1
公开(公告)日：2005-04-28
申请号：US10927949
申请日：2004-08-27
申请人： Christian Arndt , Veli Kartal , Rainald Sander
发明人： Christian Arndt , Veli Kartal , Rainald Sander
IPC分类号： H01L23/62 , H01L27/02 , H03K17/082 , H03L5/00
CPC分类号： H03K17/0822 , H01L23/62 , H01L24/48 , H01L27/0255 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/12035 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor The present invention relates to a circuit arrangement having the following features: a load transistor (T) having a control connection (G) and a first and second load connection (D, S), a drive connection (IN) coupled to the control connection (G) of the load transistor (T) and serving for the application of a drive signal (Sin), a voltage limiting circuit (10) connected between one (D) of the load connections and the drive connection (G) of the transistor, a deactivation circuit (20) connected to the voltage limiting circuit (10) and serving for the deactivation of the voltage limiting circuit (10) in a manner dependent on a deactivation signal (S22; S23), which is dependent on a load current (Id) through the load transistor (T) and/or on a drive voltage (Vgs) of the load transistor (T). The invention furthermore relates to a method for driving a load transistor.
摘要翻译：具有负载晶体管的电路装置和用于驱动负载晶体管的电压限制电路和方法技术领域本发明涉及具有以下特征的电路装置：具有控制连接（G）的负载晶体管（T）和第一和第二负载连接（D，S），耦合到负载晶体管（T）的控制连接（G）并且用于施加驱动信号（Sin）的驱动连接（IN），电压限制电路（10）负载连接的一个（D）和晶体管的驱动连接（G），连接到电压限制电路（10）的停用电路（20）并且以一种方式用于禁止电压限制电路（10）取决于通过负载晶体管（T）和/或负载晶体管（T）的驱动电压（Vgs）的负载电流（Id）的去激活信号（S22; S23）。本发明还涉及用于驱动负载晶体管的方法。

4. 发明授权

US08254070B2 Vehicle on-board electric power system 有权
标题翻译：车载电力系统
公开(公告)号：US08254070B2
公开(公告)日：2012-08-28
申请号：US11803844
申请日：2007-05-15
申请人： Christian Arndt , Alfons Graf
发明人： Christian Arndt , Alfons Graf
IPC分类号： H02H9/04
CPC分类号： H02H9/041 , B60R16/03 , H03K17/0822 , H03K17/145
摘要： A vehicle on-board electric power system is disclosed including at least one field-effect-controlled power transistor which applies a vehicle on-board electric power system supply voltage VBB to a load when actuated by a logic circuit. The power transistor has a drain-source breakdown voltage VDS with a positive temperature coefficient TKDS and is provided with a clamping means for protecting against overvoltages VO occurring in the vehicle on-board electric power system. The clamping means has a clamping voltage VCLAMP with a positive temperature coefficient TKCLAMP≈TKDS, the clamping voltage VCLAMP being lower than or equal to an anticipated maximum overvoltage VOmax in the vehicle on-board electric power system.
摘要翻译：公开了一种车载电力系统，包括至少一个场效应控制的功率晶体管，其在由逻辑电路驱动时将车载电力系统电源电压VBB施加到负载。功率晶体管具有正温度系数TKDS的漏极 - 源极击穿电压VDS，并且具有用于防止在车载电力系统中发生的过电压VO的钳位装置。夹紧装置具有正温度系数TKCLAMP≈TKDS的钳位电压VCLAMP，钳位电压VCLAMP低于或等于车载电力系统中的预期最大过电压VOmax。

5. 发明授权

US08710894B2 Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor 有权
标题翻译：具有负载晶体管的电路装置和用于驱动负载晶体管的电压限制电路和方法
公开(公告)号：US08710894B2
公开(公告)日：2014-04-29
申请号：US13423121
申请日：2012-03-16
申请人： Christian Arndt , Veli Kartal , Rainald Sander
发明人： Christian Arndt , Veli Kartal , Rainald Sander
IPC分类号： H03K5/08
CPC分类号： H03K17/0822 , H01L23/62 , H01L24/48 , H01L27/0255 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/12035 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.
摘要翻译：本发明涉及具有以下特征的电路装置：具有控制连接和第一和第二负载连接的负载晶体管; 耦合到负载晶体管的控制连接并用于施加驱动信号的驱动连接; 连接在负载连接之一和晶体管的驱动连接之间的电压限制电路; 以及去激活电路，其连接到所述电压限制电路并且以取决于取消激活信号的方式停止所述电压限制电路，所述去激活信号取决于通过所述负载晶体管的负载电流和/或所述负载的驱动电压晶体管。

6. 发明授权

US07746616B2 Protection circuit and method of protecting a load circuit 有权
标题翻译：保护电路和保护负载电路的方法
公开(公告)号：US07746616B2
公开(公告)日：2010-06-29
申请号：US11536464
申请日：2006-09-28
申请人： Christian Arndt
发明人： Christian Arndt
IPC分类号： H02H3/08 , H02H5/04 , H02H9/02
CPC分类号： H03K17/08142 , H03K17/0822 , H03K2017/0806
摘要： A protection circuit includes an interruption device formed to interrupt a current path between a protection circuit input and a protection circuit output upon exceeding a predetermined temperature at a temperature measurement location, and a control device formed to generate a control signal depending on a current in the current path, wherein the protection circuit is formed to increase the temperature at the temperature measurement location or decrease the predetermined temperature, when the control signal indicates that the current in the current path is higher than a threshold value current.
摘要翻译：保护电路包括中断装置，其形成为在温度测量位置处超过预定温度时中断保护电路输入和保护电路输出之间的电流路径;以及控制装置，其被形成为根据在电流路径，其中当控制信号指示电流路径中的电流高于阈值电流时，形成保护电路以增加温度测量位置处的温度或降低预定温度。

7. 发明授权

US07466150B2 Apparatus and method for generating a power signal from a load current 有权
标题翻译：从负载电流产生功率信号的装置和方法
公开(公告)号：US07466150B2
公开(公告)日：2008-12-16
申请号：US11536766
申请日：2006-09-29
申请人： Christian Arndt , Wolfgang Troeger
发明人： Christian Arndt , Wolfgang Troeger
IPC分类号： G01R27/08 , G01R31/327
CPC分类号： H03K17/18 , H03K17/0822 , H03K17/687
摘要： An apparatus for generating a power signal from a load current is described, has a controller with a load current input, a load current output, an intermediate signal output, and a status signal output, an influencing device with an intermediate signal input and a power signal output, and an interruption device with an interrupt input, an interrupt output, and a status signal input. The controller generates a status signal and an intermediate signal depending on the load current, and the interruption device interrupts the power signal if the status signal satisfies a predetermined first condition, and otherwise lets the power signal pass, and the influencing device generates the intermediate signal as the power signal and output the same at the power signal output if the intermediate signal does not satisfy a predetermined second condition, and otherwise generates and output a power signal with a predetermined value.
摘要翻译：描述了一种用于从负载电流产生电力信号的装置，具有负载电流输入，负载电流输出，中间信号输出和状态信号输出的控制器，具有中间信号输入和功率的影响装置信号输出，以及具有中断输入，中断输出和状态信号输入的中断装置。控制器根据负载电流产生状态信号和中间信号，如果状态信号满足预定的第一条件，则中断装置中断电源信号，否则使电源信号通过，影响装置产生中间信号作为功率信号，并且如果中间信号不满足预定的第二条件，则在功率信号输出端输出相同的信号，否则产生并输出具有预定值的功率信号。

8. 发明授权

US06819227B2 Acoustic signal generator, and method for generating an acoustic signal 有权
标题翻译：声信号发生器，以及用于产生声信号的方法
公开(公告)号：US06819227B2
公开(公告)日：2004-11-16
申请号：US10062058
申请日：2002-02-01
申请人： Christian Arndt
发明人： Christian Arndt
IPC分类号： G08B300
CPC分类号： B06B1/0261 , B06B2201/40 , B06B2201/53 , G10K9/13
摘要： An acoustic signal generator, and a method for generating an acoustic signal are described. The acoustic signal generator has a membrane that can oscillate, a deflection sensor for detecting any deflection of the membrane, an exciter configuration that is coupled to the membrane, and a power semiconductor switch with a load path that is connected to the exciter configuration. The switch has a drive connection. A drive circuit has a first connection connected to the drive connection of the power semiconductor switch and at which a drive signal is available. The drive circuit further has a second connection, to which the deflection sensor is connected.
摘要翻译：一种声信号发生器，以及一种用于产生声信号的方法。声信号发生器具有能够振荡的膜，用于检测膜的任何偏转的偏转传感器，耦合到膜的激励器配置，以及具有连接到激励器配置的负载路径的功率半导体开关。交换机有一个驱动器连接。驱动电路具有连接到功率半导体开关的驱动连接并且驱动信号可用的第一连接。驱动电路还具有连接偏转传感器的第二连接。

9. 发明授权

US06784091B1 Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices 有权
标题翻译：无磁阵列保护工艺流程，用于在磁性随机存取存储器件中形成互连通孔
公开(公告)号：US06784091B1
公开(公告)日：2004-08-31
申请号：US10250133
申请日：2003-06-05
申请人： Joachim Nuetzel , Christian Arndt , Greg Costrini , Michael C. Gaidis , Xian Jay Ning
发明人： Joachim Nuetzel , Christian Arndt , Greg Costrini , Michael C. Gaidis , Xian Jay Ning
IPC分类号： H01L2128
CPC分类号： H01L27/222 , B82Y10/00 , H01L21/76802 , H01L27/228
摘要： A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.
摘要翻译：用于在磁随机存取存储器（MRAM）器件中形成互连结构的方法包括在较低金属化层级上定义磁隧道结（MTJ）堆叠的阵列。封装介电层形成在MTJ叠层阵列和下金属化层上。然后，在密封介电层中限定通孔，并且在封装介电层上方和通孔开口内沉积平面层间电介质（ILD）层。然后在ILD层内，在MTJ堆叠阵列和通孔开口上形成开口。

10. 发明授权

US06594191B2 Segmented write line architecture 失效
标题翻译：分段写行架构
公开(公告)号：US06594191B2
公开(公告)日：2003-07-15
申请号：US10016859
申请日：2001-12-13
申请人： Stefan Lammers , Christian Arndt
发明人： Stefan Lammers , Christian Arndt
IPC分类号： G11C700
CPC分类号： G11C11/16
摘要： This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a selected segment get a high hard axis field generated by a write line current. Memory cells of deselected segments do not receive this hard axis field. This prevents an undesired state change in particularly sensitive memory cells.
摘要翻译：本发明提出了一种用于写磁层随机存取存储器（MRAM）的新型写入线分割架构。只有所选段中的存储单元才能获得由写入线电流产生的高硬轴字段。取消选择的段的存储单元不接收该硬轴字段。这防止在特别敏感的存储器单元中的不期望的状态改变。

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