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21. 发明申请

US20070183226A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20070183226A1
公开(公告)日：2007-08-09
申请号：US11717080
申请日：2007-03-13
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

22. 发明授权

US07200054B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07200054B2
公开(公告)日：2007-04-03
申请号：US11156648
申请日：2005-06-21
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，并且内部电压被提供给内部电路。

23. 再颁专利

USRE44229E1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：USRE44229E1
公开(公告)日：2013-05-21
申请号：US13365453
申请日：2012-02-03
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，并且内部电压被提供给内部电路。

24. 再颁专利

USRE43222E1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：USRE43222E1
公开(公告)日：2012-03-06
申请号：US12822839
申请日：2010-06-24
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，内部电压被提供给内部电路。

25. 发明授权

US07663897B2 Semiconductor circuit device and data processing system 失效
标题翻译：半导体电路设备和数据处理系统
公开(公告)号：US07663897B2
公开(公告)日：2010-02-16
申请号：US12068607
申请日：2008-02-08
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： H02M3/06 , G05F1/40
CPC分类号： G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要： Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.
摘要翻译：限制在接通电源时与降压动作相关的电源噪声的发生。降压单元设置有开关电容器型降压电路和串联调节器型降压电路，降压电路的降压电压输出端子共同连接。两个降压电路的降压电压输出端子的共同连接使得两者的并联驱动成为可能的两者的选择性驱动，或者是两者的连续驱动。在连续驱动中，即使在驱动串联调节器型降压电路之后驱动开关电容器型降压电路以向负载提供降压电压，开关电容器型降压电路仅需要由于负载而被补偿放电，并且可以将电容器的充电电流的峰值保持为低。当开关电容器型降压电路的工作开始时，不产生大的冲击电流，并且抑制噪声的发生。

26. 发明申请

US20060132417A1 Semiconductor integrated circuit for liquid crystal display driver 审中-公开
标题翻译：半导体集成电路用于液晶显示驱动
公开(公告)号：US20060132417A1
公开(公告)日：2006-06-22
申请号：US11311161
申请日：2005-12-20
申请人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
发明人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3674 , G09G3/3685
摘要： In a liquid crystal drive controller formed as a semiconductor integrated circuit having therein a power source circuit including a boosting circuit and driving a source line and a gate line of a TFT liquid crystal panel, the number of external capacitive elements and the number of external terminals for connecting the external capacitive elements are reduced, thereby reducing the size and cost of the chip and an electronic device on which the chip is mounted. As a boosting circuit for generating a voltage for driving a source line of the TFT liquid crystal panel in the liquid crystal controller having therein the power source including the boosting circuit, a boosting circuit having an external capacitive element is used. On the other hand, as a boosting circuit for generating a voltage for driving a gate line, a charge pump having a built-in (on-chip) capacitive element is used.
摘要翻译：在形成为半导体集成电路的液晶驱动控制器中，其中具有包括升压电路并驱动TFT液晶面板的源极线和栅极线的电源电路，外部电容元件的数量和外部端子的数量用于连接外部电容元件的功能减小，从而减小芯片的尺寸和成本以及安装芯片的电子设备。作为用于在其中具有包括升压电路的电源的液晶控制器中产生用于驱动TFT液晶面板的源极线的电压的升压电路，使用具有外部电容元件的升压电路。另一方面，作为用于产生用于驱动栅极线的电压的升压电路，使用具有内置（片上）电容元件的电荷泵。

27. 发明申请

US20050088158A1 Semiconductor circuit device and data processing system 有权
标题翻译：半导体电路设备和数据处理系统
公开(公告)号：US20050088158A1
公开(公告)日：2005-04-28
申请号：US10940379
申请日：2004-09-14
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： H01L27/04 , G05F1/40 , G05F1/56 , G05F3/24 , H01L21/822 , H01L27/02 , H02M3/07 , H03K17/16
CPC分类号： G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要： Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.
摘要翻译：限制在接通电源时与降压动作相关的电源噪声的发生。降压单元设置有开关电容器型降压电路和串联调节器型降压电路，降压电路的降压电压输出端子共同连接。两个降压电路的降压电压输出端子的共同连接使得两者的并联驱动成为可能的两者的选择性驱动，或者是两者的连续驱动。在连续驱动中，即使在驱动串联调节器型降压电路之后驱动开关电容器型降压电路以向负载提供降压电压，开关电容器类型降压电路仅需要由于负载而被补偿放电，并且可以将电容器的充电电流的峰值保持为低。当开关电容器型降压电路的工作开始时，不产生大的冲击电流，并且抑制噪声的发生。

28. 发明授权

US09360381B2 Semiconductor device and data generation method 有权
标题翻译：半导体器件和数据生成方法
公开(公告)号：US09360381B2
公开(公告)日：2016-06-07
申请号：US13439289
申请日：2012-04-04
申请人： Naoya Arisaka , Takayasu Ito , Masashi Horiguchi
发明人： Naoya Arisaka , Takayasu Ito , Masashi Horiguchi
IPC分类号： G01K7/01 , G01K15/00 , G05F3/30
CPC分类号： G01K15/005 , G01K7/01 , G05F3/30
摘要： A semiconductor device with improved temperature detection accuracy includes a coefficient calculation circuitry which calculates a plurality of N-th order coefficients, where N is an integer equal to or greater than one, of a correction function as an N-th order approximation of a characteristic function which relates temperature data measured by the temperature sensor and the actual temperature. The coefficient calculation circuitry uses N+1 pieces of the temperature data including a theoretical value at absolute zero in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature. A corrected temperatures are output using the correction function with the calculated coefficients and measured temperature values.
摘要翻译：具有改进的温度检测精度的半导体器件包括：系数计算电路，其计算多个N阶系数，其中N是等于或大于1的整数，作为特征的N阶近似的校正函数涉及由温度传感器测量的温度数据和实际温度的功能。系数计算电路使用N + 1个温度数据，包括特征函数中绝对零度的理论值和温度传感器单元在N个温度点测量的温度数据的N个测量值。使用具有计算的系数和测量的温度值的校正函数输出校正的温度。

29. 发明授权

US07821862B2 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US07821862B2
公开(公告)日：2010-10-26
申请号：US11902877
申请日：2007-09-26
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

30. 发明授权

US07693000B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07693000B2
公开(公告)日：2010-04-06
申请号：US12252241
申请日：2008-10-15
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C8/00
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在具有能够向每个存储单元输入写入数据的数据输入缓冲器的半导体器件中，在接收到对存储器单元进行的写入操作的指令之后，数据输入缓冲器从非活动状态改变为有效状态。数据输入缓冲器是具有基于SSTL的接口规范的差分输入缓冲器; 通过电源开关的导通而使其成为活动状态，从而在紧接着小振幅信号的小变化之后立即进行通过电流的流动并接收信号。由于只有在提供了写入操作对存储器单元的指令的情况下，输入缓冲器才进入活动状态，所以在提供写入操作的指令之前，预先使数据输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

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