专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US4683382A Power-saving voltage supply 失效
标题翻译：省电电源
公开(公告)号：US4683382A
公开(公告)日：1987-07-28
申请号：US667417
申请日：1984-11-01
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G05F1/46 , G05F1/56 , G11C5/14 , G11C11/407 , H03K3/01 , G06G7/10 , H03K5/153
CPC分类号： G11C5/147
摘要： In a semiconductor device according to the invention, first and second voltage dropping circuits, for generating voltages respectively having smaller values than that of an external power supply voltage, are provided. The first voltage dropping circuit, which consumes relatively less power, is always in the operative mode, and the second voltage dropping circuit, which consumes more power than that of the first voltage dropping circuit, is operated during an interval other than a standby interval. The voltages generated by the first and second voltage dropping circuits are supplied to an internal power supply line in parallel with each other.
摘要翻译：在根据本发明的半导体器件中，提供了用于产生分别具有比外部电源电压小的值的电压的第一和第二降压电路。消耗相对较少功率的第一降压电路总是处于操作模式，并且在除了待机间隔之外的间隔中操作消耗比第一降压电路多的功率的第二降压电路。由第一和第二降压电路产生的电压彼此平行地供给到内部电源线。

22. 发明授权

US4592026A Memory device resistant to soft errors 失效
标题翻译：存储器件抵抗软错误
公开(公告)号：US4592026A
公开(公告)日：1986-05-27
申请号：US564683
申请日：1983-12-23
申请人： Naohiro Matsukawa , Mitsuo Isobe , Takayasu Sakurai
发明人： Naohiro Matsukawa , Mitsuo Isobe , Takayasu Sakurai
IPC分类号： G11C11/417 , G11C7/12 , G11C7/00 , G11C11/40
CPC分类号： G11C7/12
摘要： In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.
摘要翻译：在存储器件中，多个存储器单元连接到位线对。在待机状态期间，预充电电路由芯片使能信号和地址转换检测器信号在激活状态期间控制，以将位线对充电至给定的电源电压。

23. 发明授权

US08742838B2 Stacked structure with a voltage boosting supply circuit 有权
标题翻译：具有升压电源电路的堆叠结构
公开(公告)号：US08742838B2
公开(公告)日：2014-06-03
申请号：US13123811
申请日：2009-04-17
申请人： Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
发明人： Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
IPC分类号： H01L25/00 , G05F1/46 , H02M3/145 , G11C16/30 , G11C5/14
CPC分类号： G11C5/04 , G11C5/02 , G11C5/145 , G11C11/005 , G11C16/12 , G11C16/30 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2924/0002 , H01L2924/19106 , H01L2924/00
摘要： The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.
摘要翻译：插入器30设置在通过堆叠多个DRAM芯片20和多个闪存芯片22而形成的堆叠结构24的上表面上。因此，可以实现整个装置的尺寸缩小。具有电感器的升压转换器被用作升压电路40.因此，可以实现整个装置的小型化。

24. 发明授权

US5933029A Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit 失效
标题翻译：半导体集成电路器件包括偏置电路，驱动电路和接收器电路
公开(公告)号：US5933029A
公开(公告)日：1999-08-03
申请号：US848126
申请日：1997-04-28
申请人： Tadahiro Kuroda , Takayasu Sakurai
发明人： Tadahiro Kuroda , Takayasu Sakurai
IPC分类号： H03K19/0175 , G06F12/00 , G06F13/16 , H01L27/02 , H03K19/003 , H03K19/0185 , H03K19/096 , H04L25/02 , G05F3/02 , H03K19/094
CPC分类号： H01L27/0218 , H03K19/00384 , H03K19/018507 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first/supply voltage and the second supply voltage.
摘要翻译：为了最小化功率消耗，所公开的半导体集成电路器件包括：用于产生固定在第一电源电压和第二电源电压之间的预定电压的偏置电路; 用于接收每个在第一和第二电源电压之间振动的反相输入信号和非反相输入信号的驱动器电路，用于将接收到的输入信号转换成在偏置电路的输出电压和第一电源电压之间振动的信号，并且用于通过转换的信号驱动传送路径; 用于分压偏置电路的输出电压的分压电路; 以及接收器电路，用于通过使用分压器电路的输出作为参考电压来检测用于驱动传输路径的信号，并且用于将检测到的信号转换为在第一/电源电压和第二电源电压之间振动的信号。

25. 发明授权

US4984208A Dynamic read/write memory with improved refreshing operation 失效
标题翻译：动态读/写存储器，具有改进的刷新操作
公开(公告)号：US4984208A
公开(公告)日：1991-01-08
申请号：US364529
申请日：1989-06-12
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
摘要翻译：动态读/写存储器，其中在读/写周期内执行刷新以使写恢复时间不延长。对应于当前地址的字线在写入周期内连续地进行操作。当写入操作完成时，字线被操作，从而启动刷新。字线只能在读取周期的给定时间段内运行。

26. 发明授权

US4853897A Complementary semiconductor memory device 失效
标题翻译：互补半导体存储器件
公开(公告)号：US4853897A
公开(公告)日：1989-08-01
申请号：US128946
申请日：1987-12-04
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4099
CPC分类号： G11C11/4094 , G11C11/4085 , G11C11/4099
摘要： The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.
摘要翻译：本发明公开了具有高操作可靠性的半导体存储器件。在根据本发明的半导体存储器件中，在半导体衬底中形成不同于半导体衬底的导电类型的多个阱区，并且在其它阱区中形成存储单元阵列和位线驱动器，远离彼此。通过这种布置，可以减少要连接到其上形成存储单元阵列的阱区的信号线的数量，并且可以防止在位线驱动器的操作时产生的少数载流子的不利影响。利用这种布置，阱偏压仅可应用于存储单元阵列。结果，可以提高半导体存储器件的操作可靠性。

27. 发明授权

US4682306A Self-refresh control circuit for dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件的自刷新控制电路
公开(公告)号：US4682306A
公开(公告)日：1987-07-21
申请号：US767602
申请日：1985-08-20
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A self-refresh control circuit for a dynamic memory device having memory cells and a self-refresh circuit on a single chip. The circuit includes a leak current monitor circuit representing the leakage of a memory cell and an inverter circuit for detecting the leakage of the monitor circuit so as to control the refresh operation automatically.
摘要翻译：一种用于在单个芯片上具有存储单元和自刷新电路的动态存储器件的自刷新控制电路。电路包括表示存储单元泄漏的泄漏电流监视电路和用于检测监视电路的泄漏的逆变器电路，以便自动控制刷新操作。

28. 发明授权

US4587638A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4587638A
公开(公告)日：1986-05-06
申请号：US630115
申请日：1984-07-12
申请人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Tetsuya Iizuka , Takayuki Ohtani , Akira Aono
发明人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Tetsuya Iizuka , Takayuki Ohtani , Akira Aono
IPC分类号： G11C29/00 , G11C7/02
CPC分类号： G11C29/84 , G11C29/832
摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.
摘要翻译：在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。因此，不选择具有缺陷部分的存储单元。

29. 发明申请

US20120182064A1 VOLTAGE CHARACTERISTIC REGULATING METHOD OF LATCH CIRCUIT, VOLTAGE CHARACTERISTIC REGULATING METHOD OF SEMICONDUCTOR DEVICE, AND VOLTAGE CHARACTERISTIC REGULATOR OF LATCH CIRCUIT 失效
标题翻译：电压电路的特性调节方法，半导体器件的电压特性调节方法和电压电路特性调节器
公开(公告)号：US20120182064A1
公开(公告)日：2012-07-19
申请号：US13377009
申请日：2010-06-11
申请人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
发明人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C11/413
摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要翻译：电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对导通晶体管的栅极和半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善。

30. 发明申请

US20110260781A1 INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路设备
公开(公告)号：US20110260781A1
公开(公告)日：2011-10-27
申请号：US13123811
申请日：2009-04-17
申请人： Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
发明人： Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
IPC分类号： G05F1/10
CPC分类号： G11C5/04 , G11C5/02 , G11C5/145 , G11C11/005 , G11C16/12 , G11C16/30 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2924/0002 , H01L2924/19106 , H01L2924/00
摘要： The interposer is disposed on an upper surface of the stacked structure formed by stacking a plurality of a DRAM chip and a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished in comparison to a voltage boost circuit using a charge pump connected in parallel with a plurality of a capacitance.
摘要翻译：插入器设置在通过堆叠多个DRAM芯片和多个闪存芯片而形成的层叠结构的上表面。因此，完成整个装置的尺寸减小。具有电感器的升压转换器被用作升压电路。因此，与使用与多个电容并联连接的电荷泵的升压电路相比，整个装置的尺寸比较小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式