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21. 发明申请

US20120031476A1 COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL 有权
标题翻译：组合梯形带隙异质细胞
公开(公告)号：US20120031476A1
公开(公告)日：2012-02-09
申请号：US12849966
申请日：2010-08-04
申请人： Stephen W. Bedell , Harold J. Hovel , Daniel A. Inns , Jee H. Kim , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Harold J. Hovel , Daniel A. Inns , Jee H. Kim , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L31/0352 , H01L31/18
CPC分类号： H01L31/065 , H01L31/03765 , H01L31/075 , H01L31/18 , Y02E10/548
摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.
摘要翻译：光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层半导体材料层。第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体第一和第二组成梯度半导体材料层中的材料层。光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

22. 发明申请

US20080258220A1 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 有权
标题翻译：用于改进现场效应晶体管的原位或原位热处理组合的离子植入
公开(公告)号：US20080258220A1
公开(公告)日：2008-10-23
申请号：US12128040
申请日：2008-05-28
申请人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
发明人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/8234
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

23. 发明授权

US08039371B2 Reduced defect semiconductor-on-insulator hetero-structures 有权
标题翻译：减少缺陷绝缘体上的半导体异质结构
公开(公告)号：US08039371B2
公开(公告)日：2011-10-18
申请号：US12496006
申请日：2009-07-01
申请人： Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02639 , H01L21/02647 , H01L21/76283
摘要： A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor -on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on -insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.
摘要翻译：绝缘体上半导体异质结构和制造半导体绝缘体异质结构的方法包括晶体衬底和位于其上的具有暴露结晶衬底的孔的电介质层。半导体在 - 绝缘体异质结构和用于制造绝缘体上半导体异质结构的方法还包括组成不同于位于孔内和介电层上的晶体衬底的组成的半导体层。定位在孔径上方的半导体层的一部分包括缺陷。位于电介质层上的半导体层的一部分不包括缺陷。在去除位于孔上对准的半导体层的部分之后，形成了缺陷半导体绝缘体上异质结构。

24. 发明申请

US20110001167A1 REDUCED DEFECT SEMICONDUCTOR-ON-INSULATOR HETERO-STRUCTURES 有权
标题翻译：减少缺陷半导体绝缘体异质结构
公开(公告)号：US20110001167A1
公开(公告)日：2011-01-06
申请号：US12496006
申请日：2009-07-01
申请人： Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L29/267 , H01L29/165 , H01L29/161 , H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02639 , H01L21/02647 , H01L21/76283
摘要： A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.
摘要翻译：绝缘体上半导体异质结构和制造绝缘体上半导体异质结构的方法包括晶体衬底和位于其上的具有曝光晶体衬底的孔的电介质层。绝缘体上半导体异质结构和制造绝缘体上半导体异质结构的方法还包括组成不同于位于孔内和介电层上的晶体衬底的组成的半导体层。定位在孔径上方的半导体层的一部分包括缺陷。位于电介质层上的半导体层的一部分不包括缺陷。在去除位于孔上对准的半导体层的部分之后，形成了缺陷半导体绝缘体上异质结构。

25. 发明授权

US07833884B2 Strained semiconductor-on-insulator by Si:C combined with porous process 有权
标题翻译：通过Si：C结合多孔工艺应变绝缘体上的半导体
公开(公告)号：US07833884B2
公开(公告)日：2010-11-16
申请号：US11934479
申请日：2007-11-02
申请人： Stephen W. Bedell , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/20
CPC分类号： H01L21/76245 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02236 , H01L21/02238 , H01L21/02258 , H01L21/02337 , H01L21/3167
摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的方法。该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

26. 发明授权

US08809168B2 Growing compressively strained silicon directly on silicon at low temperatures 有权
标题翻译：在低温下直接在硅上生长压缩应变硅
公开(公告)号：US08809168B2
公开(公告)日：2014-08-19
申请号：US13037944
申请日：2011-03-01
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L21/20 , H01L29/02
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.
摘要翻译：使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。在这样的生长过程中氢稀释可以变化以提供应变梯度。

27. 发明授权

US08653360B2 Compositionally-graded band gap heterojunction solar cell 有权
标题翻译：组分梯度带隙异质结太阳能电池
公开(公告)号：US08653360B2
公开(公告)日：2014-02-18
申请号：US12849966
申请日：2010-08-04
申请人： Stephen W. Bedell , Harold J. Hovel , Daniel A. Inns , Jee H. Kim , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Harold J. Hovel , Daniel A. Inns , Jee H. Kim , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L31/065 , H01L31/03765 , H01L31/075 , H01L31/18 , Y02E10/548
摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.
摘要翻译：光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层半导体材料层。第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体第一和第二组成梯度半导体材料层中的材料层。光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

28. 发明申请

US20130193483A1 Mosfet Structures Having Compressively Strained Silicon Channel 审中-公开
标题翻译：具有压缩应变硅通道的Mosfet结构
公开(公告)号：US20130193483A1
公开(公告)日：2013-08-01
申请号：US13359858
申请日：2012-01-27
申请人： Stephen W. Bedell , Kangguo Cheng , Bahman Hekmatshoartabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Kangguo Cheng , Bahman Hekmatshoartabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/41783 , H01L29/7848
摘要： MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.
摘要翻译：提供具有压缩应变硅通道的MOSFET结构。提供一种半导体器件，其包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构，其中所述场效应晶体管结构包括形成在所述栅极堆叠下方的沟道; 以及在所述硅衬底的至少一部分上的压缩应变硅层，以压缩所述通道。

29. 发明授权

US08354694B2 CMOS transistors with stressed high mobility channels 有权
标题翻译：具有应力高移动性通道的CMOS晶体管
公开(公告)号：US08354694B2
公开(公告)日：2013-01-15
申请号：US12855738
申请日：2010-08-13
申请人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.
摘要翻译：形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域。在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成，使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

30. 发明申请

US20090117720A1 STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS 有权
标题翻译：通过与多孔工艺组合的Si：C的应变半导体绝缘体
公开(公告)号：US20090117720A1
公开(公告)日：2009-05-07
申请号：US11934479
申请日：2007-11-02
申请人： Stephen W. Bedell , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/36
CPC分类号： H01L21/76245 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02236 , H01L21/02238 , H01L21/02258 , H01L21/02337 , H01L21/3167
摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的方法。该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

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