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21. 发明申请

US20050248596A1 Apparatus and method for increasing pixel resolution of image using coherent sampling 有权
标题翻译：使用相干采样增加图像像素分辨率的装置和方法
公开(公告)号：US20050248596A1
公开(公告)日：2005-11-10
申请号：US11103532
申请日：2005-04-12
申请人： Sterling Smith , Jiunn-Kuang Chen
发明人： Sterling Smith , Jiunn-Kuang Chen
IPC分类号： G09G3/36 , G09G5/00 , G09G5/37
CPC分类号： H04N7/0117 , G09G5/005 , G09G2340/0407
摘要： An apparatus and method for adjusting the pixel resolution of an input image is disclosed. According to the present invention, the pixel resolution of the input image is adjusted by oversampling an analog signal representative of the input image at a higher frequency than the pixel rate of the original image, then digitally downscaling to the desired horizontal resolution of an output image. The horizontally downscaled image is then stored in a buffer memory and subsequently scaled up to the desired vertical resolution of the output image. Preferably, oversampling of the analog signal is performed at a frequency that is an integer multiple of the input pixel rate, thus providing coherent sampling to help avoid aliasing artifacts in the sampled image.
摘要翻译：公开了一种用于调整输入图像的像素分辨率的装置和方法。根据本发明，通过以比原始图像的像素速率更高的频率对代表输入图像的模拟信号进行过采样来调整输入图像的像素分辨率，然后数字地缩小到输出图像的期望的水平分辨率。然后将水平缩小的图像存储在缓冲存储器中，并随后按比例增大到输出图像的期望垂直分辨率。优选地，在以输入像素速率的整数倍的频率处执行模拟信号的过采样，从而提供相干采样以帮助避免采样图像中的混叠伪影。

22. 发明申请

US20050093634A1 CLOCK GENERATOR AND RELATED BIASING CIRCUIT 有权
标题翻译：时钟发生器和相关偏置电路
公开(公告)号：US20050093634A1
公开(公告)日：2005-05-05
申请号：US10904269
申请日：2004-11-02
申请人： Sterling Smith , Horng-Der Chang
发明人： Sterling Smith , Horng-Der Chang
IPC分类号： G06F1/04 , H03K3/011 , H03K3/03 , H03L1/02 , H03L7/08 , H03L7/099 , H03L7/00
CPC分类号： H03K3/011 , H03K3/0315 , H03L1/022 , H03L7/08
摘要： A clock generator capable of providing low-jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.
摘要翻译：引入了能够在不利用晶体振荡器的情况下提供低抖动时钟信号的时钟发生器。本发明的时钟发生器利用相关偏置电路中的二极管，使得由于低的闪烁噪声和二极管两端的电压的低热噪声，产生的电流控制振荡器的控制电流是稳定和清晰的。利用本发明的时钟发生器代替晶体振荡器的PLL系统的成本降低。也引入了采用的偏置电路。

23. 发明授权

US06841981B2 Radio frequency data communication device in CMOS process 有权
标题翻译： CMOS工艺中的射频数据通信装置
公开(公告)号：US06841981B2
公开(公告)日：2005-01-11
申请号：US10409125
申请日：2003-04-09
申请人： Sterling Smith , Henry Tin-Hang Yung
发明人： Sterling Smith , Henry Tin-Hang Yung
IPC分类号： G06K19/07 , G11C5/14 , H04B1/00 , G05F3/04
CPC分类号： G06K19/0723 , G06K19/0713 , G11C5/142 , H04B5/0062 , H04B7/086 , Y02D70/166 , Y02D70/42 , Y02D70/444
摘要： The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.
摘要翻译：本发明提供一种具有片上电荷泵的无源RFID芯片，用于从射频产生芯片的电力。无源RFID芯片包括模拟部分和数字部分。模拟部分主要包括电压传感器和AM数据检测器。数字部分包括状态机数字逻辑控制器。进入的RF信号通过外部天线进入芯片。 RF信号由具有电压传感器的RF-DC转换器转换成稳定的DC信号。 RF-DC转换器为所有片上组件提供电源，因此芯片不需要外部电源。输入的RF信号由解调器进行解调，并进入检测到包络转换的AM数据检测器。提供电压报警，以确保电压电平不会下降到芯片的运行水平以下。逻辑信号和编程数据由状态机数字逻辑控制器控制，定时信号由片上振荡器提供。

24. 发明授权

US08456209B2 Delay locked loop and associated method 有权
标题翻译：延迟锁定环路和相关方法
公开(公告)号：US08456209B2
公开(公告)日：2013-06-04
申请号：US12956138
申请日：2010-11-30
申请人： Chun-Chia Chen , Sterling Smith
发明人： Chun-Chia Chen , Sterling Smith
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator generates a pulse signal and a determination signal according to an input clock signal. The delay unit delays the pulse signal according to a digital control signal to generate a delayed pulse signal. The phase detector detects a time delay of the delayed pulse signal according to the determination signal to generate a detection result. The control unit generates a digital control signal according to the detection result to control the delayed pulse signal by a delay amount.
摘要翻译：延迟锁定环包括脉冲发生器，延迟单元，相位检测器和控制单元。脉冲发生器根据输入时钟信号产生脉冲信号和确定信号。延迟单元根据数字控制信号延迟脉冲信号以产生延迟的脉冲信号。相位检测器根据确定信号检测延迟的脉冲信号的时间延迟，以产生检测结果。控制单元根据检测结果生成数字控制信号，以将延迟的脉冲信号控制一个延迟量。

25. 发明授权

US08339175B2 Phase generating apparatus and method thereof 有权
标题翻译：相位生成装置及其方法
公开(公告)号：US08339175B2
公开(公告)日：2012-12-25
申请号：US12957524
申请日：2010-12-01
申请人： Hsian-Feng Liu , Sterling Smith
发明人： Hsian-Feng Liu , Sterling Smith
IPC分类号： H03K3/00
CPC分类号： H03K5/13 , H03K5/135 , H03K2005/00052 , H03K2005/00058
摘要： A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock.
摘要翻译：相位产生装置根据数字信号产生具有期望相位的输出时钟。该装置包括相位选择单元和相位产生单元。相位选择单元根据数字信号的位的一部分选择多个输入时钟中的一个，以生成参考时钟。每个输入时钟分别具有差分相位。相位选择单元对参考时钟的频率进行分频，并且根据数字信号的另一部分位置选择性地延迟分频参考时钟以产生输出时钟。

26. 发明申请

US20110131354A1 Apparatus and Method of Generating Universal Memory I/O 有权
标题翻译：生成通用存储器I / O的装置和方法
公开(公告)号：US20110131354A1
公开(公告)日：2011-06-02
申请号：US12947966
申请日：2010-11-17
申请人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
发明人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
IPC分类号： G06F13/38
CPC分类号： G06F17/5068
摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.
摘要翻译：通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。定义模块根据多个I / O的引脚配置来定义映射表。映射表包括多个IO和多个存储器功能之间的对应关系。检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索对应于映射表的控制信息。生成模块根据控制信息生成硬件描述语言（HDL）文件。布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

27. 发明申请

US20110063155A1 Sigma-Delta Modulator with Shared Operational Amplifier and Associated Method 有权
标题翻译：具有共享运算放大器和相关方法的Σ-Δ调制器
公开(公告)号：US20110063155A1
公开(公告)日：2011-03-17
申请号：US12861970
申请日：2010-08-24
申请人： Jianqiu Chen , Sterling Smith , Jianping Cheng
发明人： Jianqiu Chen , Sterling Smith , Jianping Cheng
IPC分类号： H03M3/00
CPC分类号： H03M3/474 , H03M3/456
摘要： A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.
摘要翻译：具有共享运算放大器（运算放大器）的Σ-Δ调制器包括集成电路，具有共享运算放大器的两个积分器，能够集成两个积分器的两个输入信号; 多个量化器，耦合到积分电路，用于将积分器的输出信号与预定信号进行比较，然后产生数字输出信号; 分别耦合到量化器的多个DAC，用于将数字输出信号转换为模拟反馈信号到积分器; 以及用于向积分电路和量化器提供时钟信号的时钟发生器。因此，由于共享运算放大器，调制器的布局面积和功耗降低。

28. 发明申请

US20090243679A1 Semi-Digital Delay Locked Loop Circuit and Method 有权
标题翻译：半数字延迟锁定环路和方法
公开(公告)号：US20090243679A1
公开(公告)日：2009-10-01
申请号：US12402815
申请日：2009-03-12
申请人： Sterling Smith , Ellen Chen Yeh , Wen cai Lu
发明人： Sterling Smith , Ellen Chen Yeh , Wen cai Lu
IPC分类号： H03L7/06 , H03L7/00 , H03H11/16
CPC分类号： H04N5/126 , H03L7/07 , H03L7/0814 , H03L7/0996
摘要： A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.
摘要翻译：具有自动调整锁定精度的校准机制的可扩展DLL（延迟锁定环路）电路。延迟锁定环电路包括用于根据系统时钟产生多个相位信号的多相锁相环电路，其中相位信号之一是像素时钟; 相位检测器，用于根据像素时钟检测参考信号和反馈信号之间的积分相位误差和分数相位误差; 相位选择器，用于根据分数相位误差选择一个相位信号; 以及延迟电路，用于根据积分相位误差和所选择的相位信号偏移参考信号的相位，以产生输出信号。

29. 发明授权

US07379726B2 AM data recovery circuit 有权
标题翻译： AM数据恢复电路
公开(公告)号：US07379726B2
公开(公告)日：2008-05-27
申请号：US11779666
申请日：2007-07-18
申请人： Sterling Smith , Henry Tin-Hang Yung
发明人： Sterling Smith , Henry Tin-Hang Yung
IPC分类号： H04B1/26 , G05F3/04
CPC分类号： G06K19/0723 , G06K19/0713 , G11C5/142 , H04B5/0062 , H04B7/086 , Y02D70/166 , Y02D70/42 , Y02D70/444
摘要： The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.
摘要翻译：本发明提供一种具有片上电荷泵的无源RFID芯片，用于从射频产生芯片的电力。无源RFID芯片包括模拟部分和数字部分。模拟部分主要包括电压传感器和AM数据检测器。数字部分包括状态机数字逻辑控制器。进入的RF信号通过外部天线进入芯片。 RF信号由具有电压传感器的RF-DC转换器转换成稳定的DC信号。 RF-DC转换器为所有片上组件提供电源，因此芯片不需要外部电源。输入的RF信号由解调器进行解调，并进入检测到包络转换的AM数据检测器。提供电压报警，以确保电压电平不会下降到芯片的运行水平以下。逻辑信号和编程数据由状态机数字逻辑控制器控制，定时信号由片上振荡器提供。

30. 发明授权

US07310397B2 Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions 有权
标题翻译：数据恢复电路，相位检测电路及相位条件检测与校正方法
公开(公告)号：US07310397B2
公开(公告)日：2007-12-18
申请号：US10698623
申请日：2003-11-03
申请人： Sterling Smith , Sheng-Yao Liu , Huimin Tsai
发明人： Sterling Smith , Sheng-Yao Liu , Huimin Tsai
IPC分类号： H04L7/00
CPC分类号： H04L7/0331
摘要： In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.
摘要翻译：在本发明的数据恢复电路中，第一组采样时钟脉冲被用于对输入数据流中的数据位的大部分中心部分采样以产生第一采样数据流，而第二组采样时钟脉冲是用于对输入数据流中每两个相邻数据位之间的过渡部分进行近似采样，以产生第二采样数据流。通过检测第二采样数据流中的每一比特相对于第一采样数据流中相应的两个相邻比特，相位检测和校正电路确定采样时钟的相位的早期状态或后期状态，并产生一个信号通过向后或向后移动相位来校正采样时钟的相位。根据本发明，可以使用具有较低频率的采样时钟进行采样，并且可以校正相位误差以获得正确的数据恢复。

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