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1. 发明申请

US20110131354A1 Apparatus and Method of Generating Universal Memory I/O 有权
标题翻译：生成通用存储器I / O的装置和方法
公开(公告)号：US20110131354A1
公开(公告)日：2011-06-02
申请号：US12947966
申请日：2010-11-17
申请人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
发明人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
IPC分类号： G06F13/38
CPC分类号： G06F17/5068
摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.
摘要翻译：通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。定义模块根据多个I / O的引脚配置来定义映射表。映射表包括多个IO和多个存储器功能之间的对应关系。检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索对应于映射表的控制信息。生成模块根据控制信息生成硬件描述语言（HDL）文件。布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

2. 发明授权

US08635569B2 Apparatus and method of generating universal memory I/O 有权
标题翻译：产生通用存储器I / O的装置和方法
公开(公告)号：US08635569B2
公开(公告)日：2014-01-21
申请号：US12947966
申请日：2010-11-17
申请人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
发明人： Sterling Smith , Hsian-Feng Liu , Eer-Wen Tyan , Chun-Chia Chen , Ming-Chieh Yeh , Chung-Ching Chen , Yo-Lin Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.
摘要翻译：通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。定义模块根据多个I / O的引脚配置来定义映射表。映射表包括多个IO和多个存储器功能之间的对应关系。检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索与映射表相对应的控制信息。生成模块根据控制信息生成硬件描述语言（HDL）文件。布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

3. 发明申请

US20110153963A1 Memory Controller and Associated Control Method 有权
标题翻译：内存控制器和相关控制方法
公开(公告)号：US20110153963A1
公开(公告)日：2011-06-23
申请号：US12976815
申请日：2010-12-22
申请人： Yo-Lin Chen , Hsian-Feng Liu , Ming-Chieh Yeh
发明人： Yo-Lin Chen , Hsian-Feng Liu , Ming-Chieh Yeh
IPC分类号： G06F12/02
CPC分类号： G06F13/161 , G06F13/1673
摘要： A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
摘要翻译：提供存储器控制器和相关联的控制方法。存储器控制器连接到存储器模块，并且包括用于接收从存储器模块输出的有效数据的FIFO缓冲器，用于指示存储在FIFO缓冲器中的写入数据的写指针和用于指示存储在FIFO中的读数据的读指针缓冲。根据该控制方法，在生成读取命令之后的存储器模块的CAS等待时间期间，写入指针的值被控制为具有与读取指针相同的值。

4. 发明授权

US08412883B2 Memory controller and associated control method 有权
标题翻译：内存控制器及相关控制方式
公开(公告)号：US08412883B2
公开(公告)日：2013-04-02
申请号：US12976815
申请日：2010-12-22
申请人： Yo-Lin Chen , Hsian-Feng Liu , Ming-Chieh Yeh
发明人： Yo-Lin Chen , Hsian-Feng Liu , Ming-Chieh Yeh
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1673
摘要： A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
摘要翻译：提供存储器控制器和相关联的控制方法。存储器控制器连接到存储器模块，并且包括用于接收从存储器模块输出的有效数据的FIFO缓冲器，用于指示存储在FIFO缓冲器中的写入数据的写指针和用于指示存储在FIFO中的读数据的读指针缓冲。根据该控制方法，在生成读取命令之后的存储器模块的CAS等待时间期间，写入指针的值被控制为具有与读取指针相同的值。

5. 发明申请

US20110158005A1 Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks 有权
标题翻译：数据访问装置和使用内部生成时钟访问数据的相关方法
公开(公告)号：US20110158005A1
公开(公告)日：2011-06-30
申请号：US12968719
申请日：2010-12-15
申请人： Eer-Wen Tyan , Ming-Chieh Yeh , Yi Ling Chen
发明人： Eer-Wen Tyan , Ming-Chieh Yeh , Yi Ling Chen
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/22 , G11C2207/2254
摘要： The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.
摘要翻译：数据存取装置包括锁相环（PLL）和数据接收电路。 PLL提供多个内部时钟并根据相位选择信号从多个内部时钟中选择选通时钟。数据接收电路包括锁存模块，用于根据选通时钟的触发锁存数据信号和校准电路，用于产生相位选择信号，用于在训练中的多个内部时钟处将数据与预定数据进行匹配模式，并最终确定与在正常模式中使用的优选时钟相对应的相位选择信号。

6. 发明授权

US08482293B2 I/O circuit calibration method and associated apparatus 有权
标题翻译： I / O电路校准方法及相关设备
公开(公告)号：US08482293B2
公开(公告)日：2013-07-09
申请号：US12889017
申请日：2010-09-23
申请人： Eer-Wen Tyan , Ming-Chieh Yeh
发明人： Eer-Wen Tyan , Ming-Chieh Yeh
IPC分类号： G01R35/00
CPC分类号： H04L25/029
摘要： An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.
摘要翻译：提供I / O校准方法和装置，用于校准芯片中的I / O电路的输出端的驱动阻抗。芯片还包括多个基本阻抗和非易失性存储器。 I / O电路校准方法包括：测量一个基本阻抗的阻抗值，并将测得的阻抗值记录在非易失性存储器中; 通过选择性地传导基本阻抗来合成校准阻抗; 调整校准阻抗中传导的基本阻抗的数量，并根据测量结果估计驱动阻抗的阻抗值，并将电压除以校准阻抗和输出端的驱动阻抗。

7. 发明授权

US08395946B2 Data access apparatus and associated method for accessing data using internally generated clocks 有权
标题翻译：数据访问装置和使用内部生成的时钟访问数据的相关方法
公开(公告)号：US08395946B2
公开(公告)日：2013-03-12
申请号：US12968719
申请日：2010-12-15
申请人： Eer-Wen Tyan , Ming-Chieh Yeh , Yi Ling Chen
发明人： Eer-Wen Tyan , Ming-Chieh Yeh , Yi Ling Chen
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C7/22 , G11C2207/2254
摘要： The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.
摘要翻译：数据存取装置包括锁相环（PLL）和数据接收电路。 PLL提供多个内部时钟并根据相位选择信号从多个内部时钟中选择选通时钟。数据接收电路包括锁存模块，用于根据选通时钟的触发锁存数据信号和校准电路，用于根据多个内部时钟产生用于使数据与预定数据匹配的相位选择信号训练模式，最后确定对应于在正常模式中使用的优选时钟的相位选择信号。

8. 发明申请

US20110074520A1 I/O Circuit Calibration Method and Associated Apparatus 有权
标题翻译： I / O电路校准方法及相关设备
公开(公告)号：US20110074520A1
公开(公告)日：2011-03-31
申请号：US12889017
申请日：2010-09-23
申请人： Eer-Wen Tyan , Ming-Chieh Yeh
发明人： Eer-Wen Tyan , Ming-Chieh Yeh
IPC分类号： H03H7/38
CPC分类号： H04L25/029
摘要： An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.
摘要翻译：提供I / O校准方法和装置，用于校准芯片中的I / O电路的输出端的驱动阻抗。芯片还包括多个基本阻抗和非易失性存储器。 I / O电路校准方法包括：测量一个基本阻抗的阻抗值，并将测得的阻抗值记录在非易失性存储器中; 通过选择性地传导基本阻抗来合成校准阻抗; 调整校准阻抗中传导的基本阻抗的数量，并根据测量结果估计驱动阻抗的阻抗值，并将电压除以校准阻抗和输出端的驱动阻抗。

9. 发明申请

US20110001768A1 Display Controller, Video Signal Transmitting Method and System 有权
标题翻译：显示控制器，视频信号传输方法和系统
公开(公告)号：US20110001768A1
公开(公告)日：2011-01-06
申请号：US12822914
申请日：2010-06-24
申请人： Chen-Nan Lin , Ming-Chieh Yeh , Chun Wen Yeh , Chun-Chia Chen
发明人： Chen-Nan Lin , Ming-Chieh Yeh , Chun Wen Yeh , Chun-Chia Chen
IPC分类号： G09G5/02
CPC分类号： G09G3/3685 , G09G2310/0221 , G09G2310/027 , G09G2352/00
摘要： A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.
摘要翻译：提供了显示控制器，视频信号发送方法及其系统。显示控制器包括处理电路; 耦合到所述处理电路的发送信道; 耦合到所述处理电路的接收信道; 以及产生内部时钟信号和外部时钟信号的时钟发生器。在接收到视频信号时，处理电路处理视频信号的第一部分像素数据以输出第一显示控制信号。发送信道根据要输出的内部时钟信号将视频信号的第二部分像素数据转换为具有多数据速率的部分视频信号。

10. 发明授权

US09805685B2 Display controller, video signal transmitting method and system thereof for transmitting video signals with multiple data rate and reduced numbers of signals line 有权
公开(公告)号：US09805685B2
公开(公告)日：2017-10-31
申请号：US12822914
申请日：2010-06-24
申请人： Chen-Nan Lin , Ming-Chieh Yeh , Chun Wen Yeh , Chun-Chia Chen
发明人： Chen-Nan Lin , Ming-Chieh Yeh , Chun Wen Yeh , Chun-Chia Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G2310/0221 , G09G2310/027 , G09G2352/00
摘要： A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

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