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21. 发明授权

US08609534B2 Electrical fuse structure and method of fabricating same 有权
标题翻译：电熔丝结构及其制造方法
公开(公告)号：US08609534B2
公开(公告)日：2013-12-17
申请号：US12890941
申请日：2010-09-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译：使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。通孔开口位于顶部并连接到金属层。双镶嵌结构还包括线路开口和通孔开口内的导电特征。电介质间隔物也存在于线路开口和通孔开口内。介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。因此，提供了节省空间的高编程效率电熔丝。

22. 发明申请

US20130328208A1 DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
标题翻译：双重对等双向对联方案
公开(公告)号：US20130328208A1
公开(公告)日：2013-12-12
申请号：US13490542
申请日：2012-06-07
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76819 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要翻译：在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。之后形成第二电介质材料层。在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的第一条金属线。形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

23. 发明申请

US20130320411A1 BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION 审中-公开
公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
申请人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

24. 发明授权

US08592306B2 Redundant metal barrier structure for interconnect applications 有权
标题翻译：用于互连应用的冗余金属屏障结构
公开(公告)号：US08592306B2
公开(公告)日：2013-11-26
申请号：US13529389
申请日：2012-06-21
申请人： Chih-Chao Yang , Thomas M. Shaw
发明人： Chih-Chao Yang , Thomas M. Shaw
IPC分类号： H01L21/768
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.
摘要翻译：为互连结构提供冗余金属扩散屏障，从而提高互连结构的可靠性和可扩展性。冗余金属扩散阻挡层位于位于电介质材料内的开口内，并且位于扩散阻挡层和也存在于开口内的导电材料之间。冗余扩散阻挡层包括单层或多层结构，其包含Ru和包含纯Co或Co合金的含Co材料，其包括N，B和P中的至少一种。

25. 发明授权

US08492270B2 Structure for nano-scale metallization and method for fabricating same 有权
标题翻译：纳米级金属化结构及其制造方法
公开(公告)号：US08492270B2
公开(公告)日：2013-07-23
申请号：US12885665
申请日：2010-09-20
申请人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

26. 发明授权

US08487696B2 Modularized three-dimensional capacitor array 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US08487696B2
公开(公告)日：2013-07-16
申请号：US13438230
申请日：2012-04-03
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： G01R31/28 , H03K17/687
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

27. 发明授权

US08471356B2 Programmable anti-fuse structures with conductive material islands 失效
标题翻译：具有导电材料岛的可编程抗熔丝结构
公开(公告)号：US08471356B2
公开(公告)日：2013-06-25
申请号：US12761780
申请日：2010-04-16
申请人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： G06F17/50 , H01L21/768 , H01L23/525
CPC分类号： H01L23/5252 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
摘要翻译：提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

28. 发明授权

US08456006B2 Hybrid interconnect structure for performance improvement and reliability enhancement 有权
标题翻译：混合互连结构，用于性能改进和可靠性提升
公开(公告)号：US08456006B2
公开(公告)日：2013-06-04
申请号：US13174841
申请日：2011-07-01
申请人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
发明人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76841 , H01L21/7682 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要翻译：本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地，气隙。与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

29. 发明申请

US20130112462A1 Metal Alloy Cap Integration 审中-公开
标题翻译：金属合金盖整合
公开(公告)号：US20130112462A1
公开(公告)日：2013-05-09
申请号：US13290557
申请日：2011-11-07
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H05K1/09 , H05K3/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76849 , H01L21/76877 , H01L21/76882 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要翻译：包括金属合金覆盖层的金属互连结构及其制造方法。互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。因此，互连结构中的残余合金元素的电阻率冲击降低。也就是说，在金属互连结构的特征内部存在合金元素的减少。金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。

30. 发明授权

US08404582B2 Structure and method for manufacturing interconnect structures having self-aligned dielectric caps 有权
标题翻译：用于制造具有自对准电介质盖的互连结构的结构和方法
公开(公告)号：US08404582B2
公开(公告)日：2013-03-26
申请号：US12773306
申请日：2010-05-04
申请人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
摘要翻译：提供具有自对准电介质盖的互连结构。在基板上形成至少一个金属化层。电介质盖被选择性地沉积在金属化层上。

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