专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

22. 发明申请

US20140011340A1 Method of Forming a CMOS Device with a Stressed-Channel NMOS Transistor and a Strained-Channel PMOS Transistor 有权
标题翻译：用高压沟道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
公开(公告)号：US20140011340A1
公开(公告)日：2014-01-09
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译：形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

23. 发明授权

US08372750B2 Method and system for improved nickel silicide 有权
标题翻译：改善硅化镍的方法和系统
公开(公告)号：US08372750B2
公开(公告)日：2013-02-12
申请号：US12890100
申请日：2010-09-24
申请人： Amitabh Jain , Peijun Chen , Jorge A. Kittl
发明人： Amitabh Jain , Peijun Chen , Jorge A. Kittl
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823835 , H01L29/665 , H01L29/78
摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.
摘要翻译：根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域每个源极和漏极区域通过加热衬底。

24. 发明授权

US07615458B2 Activation of CMOS source/drain extensions by ultra-high temperature anneals 有权
标题翻译：通过超高温退火激活CMOS源极/漏极延伸
公开(公告)号：US07615458B2
公开(公告)日：2009-11-10
申请号：US11764980
申请日：2007-06-19
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L21/331
CPC分类号： H01L21/2652 , H01L21/2255 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/6659
摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。在栅极电介质层上形成栅电极。将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

25. 发明授权

US07511350B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07511350B2
公开(公告)日：2009-03-31
申请号：US12018313
申请日：2008-01-23
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

26. 发明申请

US20090065880A1 Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region 有权
标题翻译：使用激光退火制造的半导体器件将应力引入通道区域
公开(公告)号：US20090065880A1
公开(公告)日：2009-03-12
申请号：US11853328
申请日：2007-09-11
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/268 , H01L21/28044 , H01L29/6656 , H01L29/7843 , H01L29/7845
摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.
摘要翻译：在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热在进行激光退火之后退火。

27. 发明授权

US07297605B2 Source/drain extension implant process for use with short time anneals 有权
标题翻译：源/漏扩展植入过程用于短时间退火
公开(公告)号：US07297605B2
公开(公告)日：2007-11-20
申请号：US10842308
申请日：2004-05-10
申请人： Amitabh Jain , Gordon Pollack
发明人： Amitabh Jain , Gordon Pollack
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/26586 , H01L21/324 , H01L21/823814 , H01L29/6659 , H01L29/7833
摘要： The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).
摘要翻译：本发明在一个实施例中提供一种用于制造金属氧化物半导体（MOS）器件（100）的工艺。该方法包括在衬底（105）上形成栅极（120）并在衬底（105）中形成源极/漏极延伸部分（160）。形成源极/漏极延伸部分（160）包括异常倾斜的掺杂剂注入（135）和掺杂剂注入（145）。异常倾斜的掺杂剂注入（135）使用大于约零度的第一加速能量和倾斜角。掺杂剂注入（145）使用高于第一加速能量的第二加速能量。该工艺还包括执行衬底（105）的超高温退火，其中源极/漏极延伸部（160）的部分（170）在栅极（120）下方。

28. 发明授权

US07211516B2 Nickel silicide including indium and a method of manufacture therefor 有权
公开(公告)号：US07211516B2
公开(公告)日：2007-05-01
申请号：US11096660
申请日：2005-04-01
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

29. 发明申请

US20060163651A1 Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor 有权
标题翻译：具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法
公开(公告)号：US20060163651A1
公开(公告)日：2006-07-27
申请号：US11042415
申请日：2005-01-25
申请人： Antonio Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
发明人： Antonio Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823871
摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
摘要翻译：本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。制造晶体管器件的方法以及其它步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界。该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

30. 发明申请

US20060073656A1 Method and system for improved nickel silicide 有权
公开(公告)号：US20060073656A1
公开(公告)日：2006-04-06
申请号：US10959674
申请日：2004-10-04
申请人： Amitabh Jain , Peijun Chen , Jorge Kittl
发明人： Amitabh Jain , Peijun Chen , Jorge Kittl
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823835 , H01L29/665 , H01L29/78
摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式