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21. 发明授权

US07444497B2 Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support 有权
标题翻译：使用推测内存支持，在冗余多线程系统中管理外部内存更新以进行故障检测
公开(公告)号：US07444497B2
公开(公告)日：2008-10-28
申请号：US10750039
申请日：2003-12-30
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer , Christopher T. Weaver
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer , Christopher T. Weaver
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F11/1494 , G06F11/1497
摘要： A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
摘要翻译：公开了一种多线程体系结构，用于管理使用推测性内存支持的冗余多线程系统中的故障检测的外部存储器更新。特别地，一种方法通过使用推测性存储器支持将冗余线程从外部更新隔离，从而在SRT处理器上提供负载值的输入复制。因此，该方法避免了专用结构提供输入复制的需要。

22. 发明授权

US07308607B2 Periodic checkpointing in a redundantly multi-threaded architecture 有权
标题翻译：冗余多线程架构中的定期检查点
公开(公告)号：US07308607B2
公开(公告)日：2007-12-11
申请号：US10651388
申请日：2003-08-29
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F9/3851 , G06F9/3863
摘要： A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.
摘要翻译：具有一个或多个检查器电路的多线程架构，其操作于在复制范围之外发送数据的存储操作。用于检查复制领域的输出的故障检测机制在执行时间结束时重新用于检查点。

23. 发明授权

US6154828A Method and apparatus for employing a cycle bit parallel executing instructions 失效
标题翻译：用于使用循环位指示并行执行指令的执行完成的方法和装置
公开(公告)号：US6154828A
公开(公告)日：2000-11-28
申请号：US072632
申请日：1993-06-03
申请人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
发明人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838
摘要： A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.
摘要翻译：一种方法和装置，包括用于存储可执行文件的装置，该可执行文件包括定义与每个功能操作相关联的功能操作和周期位的一组比特，以及用于在单个执行周期期间根据单个执行周期并行地完成可变数量的功能操作的装置相关联的周期位的状态。该方法和装置消除了对复杂数据依赖性检查硬件的需要，并允许最小量的控制逻辑来完成可执行文件的执行。该方法和装置进一步最小化了对可执行文件添加空操作（NOP）的必要性，这减少了存储可执行文件所需的存储空间量，并允许在多个硬件实现上使用可执行文件，并且使用用于在单个执行周期中有多个目的。

24. 发明授权

US5420990A Mechanism for enforcing the correct order of instruction execution 失效
标题翻译：执行指令执行顺序的机制
公开(公告)号：US5420990A
公开(公告)日：1995-05-30
申请号：US79494
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3842
摘要： An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.
摘要翻译：用于执行所选指令的装置以正确的顺序执行，包括用于存储由所选择的指令从存储器读取的数据的加载地址的第一内容可寻址存储器。第一内容可寻址存储器将存储地址与要写入存储器的数据的加载地址进行比较。所述第一内容可寻址存储器产生第一信号，如果所述加载地址之一与随后比较的一个所述存储地址相同。该装置还包括第二内容可寻址存储器，用于存储和比较由所选指令读和写的数据的状态。如果存储状态之一与所述比较状态之一相同，则第二内容可寻址存储器产生第二信号。所存储的状态包括在检测到第一和第二信号时重复所选指令的执行的程序计数器。

25. 发明申请

US20100332810A1 Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions 审中-公开
标题翻译：具有指令上下文存储电路的可重构功能单元，以支持指令执行
公开(公告)号：US20100332810A1
公开(公告)日：2010-12-30
申请号：US12495604
申请日：2009-06-30
申请人： Tao Wang , Zhihong Yu , Joel S. Emer , Yuan Liu , Peng Li
发明人： Tao Wang , Zhihong Yu , Joel S. Emer , Yuan Liu , Peng Li
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3897
摘要： A functional unit is described. The functional unit includes a reconfigurable logic circuitry and instruction context storage circuitry to store instruction context information generated from instructions executed by the reconfigurable logic circuitry within the reconfigurable functional unit. The instructions include speculatively executed instructions.
摘要翻译：描述功能单元。功能单元包括可重配置逻辑电路和指令上下文存储电路，用于存储由可重构功能单元内的可重配置逻辑电路执行的指令生成的指令上下文信息。指令包括推测执行的指令。

26. 发明授权

US07747932B2 Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system 失效
标题翻译：在锁定的双模块冗余系统中减少不可纠正的错误率
公开(公告)号：US07747932B2
公开(公告)日：2010-06-29
申请号：US11173835
申请日：2005-06-30
申请人： Paul B. Racunas , Joel S. Emer , Arijit Biswas , Shubhendu S. Mukherjee , Steven E. Raasch
发明人： Paul B. Racunas , Joel S. Emer , Arijit Biswas , Shubhendu S. Mukherjee , Steven E. Raasch
IPC分类号： H03M13/00
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1658 , G06F11/1683
摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
摘要翻译：公开了用于降低锁定双模块冗余系统中的不可校正错误率的装置和方法的实施例。在一个实施例中，装置包括两个处理器核，微检查器，全局检验器和故障逻辑。微检查器是检测来自一个核心中的结构的值是否与另一个核心中的相应结构的值匹配。全局检查器是检测两个内核之间的锁步失败。如果存在锁步错误但微检查器检测到不匹配，则故障逻辑是使两个内核重新同步。

27. 发明授权

US06470443B1 Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information 失效
标题翻译：流水线多线程处理器根据计数信息在级间缓冲区中选择线程指令
公开(公告)号：US06470443B1
公开(公告)日：2002-10-22
申请号：US09526137
申请日：2000-03-14
申请人： Joel S. Emer , Rebecca Stamm , Trggve Fossum , Robert H. Halstead, Jr. , George Z. Chrysos , Dean Tullsen , Susan Eggers , Henry M. Levy
发明人： Joel S. Emer , Rebecca Stamm , Trggve Fossum , Robert H. Halstead, Jr. , George Z. Chrysos , Dean Tullsen , Susan Eggers , Henry M. Levy
IPC分类号： G06F1500
CPC分类号： G06F9/3851 , G06F9/3861
摘要： A multi-threaded processor comprising a pipeline including a number of stages processing instructions belonging to a plurality of threads. A buffer stores instructions from different ones of the threads. Count logic stores count information relating to each of the threads to indicate the number of instructions in each of the corresponding threads that have a particular attribute. A selection logic circuit has an output coupled to the buffer to determine which instruction is to be read from the buffer based on the count information stored by the count logic. The count information may, for example, provide information relating to a likelihood that one or more instructions belonging to each of the threads will be cancelled; relating to a count of unresolved branch instructions; or relating to a count of outstanding data cache misses. In operation, a thread may be selected for execution based on a selected attribute to enhance processing performance.
摘要翻译：一种多线程处理器，包括包含属于多个线程的多个级处理指令的流水线。缓冲存储来自不同线程的指令。计数逻辑存储与每个线程相关的计数信息，以指示具有特定属性的每个相应线程中的指令数。选择逻辑电路具有耦合到缓冲器的输出，以基于计数逻辑存储的计数信息来确定要从缓冲器读取哪个指令。计数信息可以例如提供与属于每个线程的一个或多个指令将被取消的可能性有关的信息; 涉及未解决的分支指示的计数; 或涉及未完成的数据高速缓存未命中的计数。在操作中，可以基于所选择的属性来选择线程以执行以增强处理性能。

28. 发明授权

US6073159A Thread properties attribute vector based thread selection in multithreading processor 失效
标题翻译：线程属性多线程处理器中基于属性向量的线程选择
公开(公告)号：US6073159A
公开(公告)日：2000-06-06
申请号：US775553
申请日：1996-12-31
申请人： Joel S. Emer , Rebecca Stamm , Trggve Fossum , Robert H. Halstead, Jr. , George Z. Chrysos , Dean Tullsen , Susan Eggers , Henry M. Levy
发明人： Joel S. Emer , Rebecca Stamm , Trggve Fossum , Robert H. Halstead, Jr. , George Z. Chrysos , Dean Tullsen , Susan Eggers , Henry M. Levy
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/3851 , G06F9/3861
摘要： A technique is provided for selecting a preferred thread from a plurality of threads executing within a simultaneous multithreaded, out-of-order execution computer system, the preferred thread possessing those instructions which, while in flight within the pipeline of the computer system provide, in contrast to those instructions belonging to other threads, a more beneficial performance of the central processing unit of the computer system. To determine the preferred thread, a technique is provided to evaluate attributes of each thread which indicate whether the thread includes a number of instructions which are likely to be cancelled while in flight or whether a thread includes instructions which will remain in the instruction queue for a number of cycles, unable to execute, thus stalling the execution of the thread to which the instruction belongs.
摘要翻译：提供了一种用于从同时多线程，无序执行计算机系统中执行的多个线程中选择优选线程的技术，所述线程拥有那些在计算机系统管线内的飞行中提供的指令，与属于其他线程的指令相反，是计算机系统的中央处理单元的更有利的性能。为了确定优选的线程，提供了一种技术来评估每个线程的属性，其指示线程是否包括在飞行中可能被取消的许多指令，或者线程是否包括将保留在指令队列中的指令循环次数，无法执行，从而停止指令所属线程的执行。

29. 发明授权

US5421022A Apparatus and method for speculatively executing instructions in a computer system 失效
标题翻译：用于在计算机系统中推测执行指令的装置和方法
公开(公告)号：US5421022A
公开(公告)日：1995-05-30
申请号：US79309
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312 , G06F9/42 , G06F9/44
CPC分类号： G06F9/3865 , G06F9/3842
摘要： A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.
摘要翻译：编译器将指令分组成集合。指令集是由编译器无法解决的数据和控制依赖关系相关的。在具有未解决的依赖性的指令集在假定不发生异常条件的假设下在计算机系统的推测状态下执行。然而，如果在推测状态下执行一组指令时发生异常情况，则检测该异常条件，并且在计算机系统的实际状态中重新执行指令集以解决异常状况。

30. 发明授权

US07373548B2 Hardware recovery in a multi-threaded architecture 有权
标题翻译：多线程架构中的硬件恢复
公开(公告)号：US07373548B2
公开(公告)日：2008-05-13
申请号：US10651523
申请日：2003-08-29
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F11/1482
摘要： Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.
摘要翻译：基于日志的硬件恢复。系统的检查点状态包括体系结构寄存器值和存储器。检查点由生成检查点时的体系结构寄存器文件值的副本组成。维护非确定性事件的有序日志，以便重复响应以模拟完整的检查点以进行错误恢复。当处理器检测到错误时，处理器从上一个检查点重新加载状态，并从日志重复非确定性事件。

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