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1. 发明授权

US07373548B2 Hardware recovery in a multi-threaded architecture 有权
标题翻译：多线程架构中的硬件恢复
公开(公告)号：US07373548B2
公开(公告)日：2008-05-13
申请号：US10651523
申请日：2003-08-29
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F11/1482
摘要： Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.
摘要翻译：基于日志的硬件恢复。系统的检查点状态包括体系结构寄存器值和存储器。检查点由生成检查点时的体系结构寄存器文件值的副本组成。维护非确定性事件的有序日志，以便重复响应以模拟完整的检查点以进行错误恢复。当处理器检测到错误时，处理器从上一个检查点重新加载状态，并从日志重复非确定性事件。

2. 发明授权

US07555703B2 Method and apparatus for reducing false error detection in a microprocessor 有权
标题翻译：用于减少微处理器中的错误检测的方法和装置
公开(公告)号：US07555703B2
公开(公告)日：2009-06-30
申请号：US10871430
申请日：2004-06-17
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
摘要翻译：减少微处理器中的错误检测的技术。通过指令流程路径，通过指令传播pi位。当检测到奇偶校验错误时，设置pi位，而不是提高机器检查异常。达到提交点后，处理器可以确定指令是否在错误的路径上。

3. 发明授权

US07543221B2 Method and apparatus for reducing false error detection in a redundant multi-threaded system 有权
标题翻译：用于减少冗余多线程系统中的错误检测的方法和装置
公开(公告)号：US07543221B2
公开(公告)日：2009-06-02
申请号：US10948813
申请日：2004-09-22
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
摘要翻译：一种在冗余多线程计算环境中减少微处理器中的错误检测的技术。通过指令流程路径，使用至少两个指令来传播pi位。比较执行指令的结果，看是否发生错误，如果是，则检查pi位，以确定哪个指令包含错误。

4. 发明授权

US07386756B2 Reducing false error detection in a microprocessor by tracking instructions neutral to errors 有权
标题翻译：通过跟踪中性到错误的指令，减少微处理器中的错误检测
公开(公告)号：US07386756B2
公开(公告)日：2008-06-10
申请号：US10871429
申请日：2004-06-17
申请人： Joel S. Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt , Christopher T. Weaver
发明人： Joel S. Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt , Christopher T. Weaver
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/0721 , G06F9/30145 , G06F9/30181 , G06F9/3865 , G06F11/0751 , G06F11/1052 , G06F11/1407
摘要： A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
摘要翻译：通过跟踪中性到错误的指令来减少微处理器中的错误检测的技术。当指令被解码时，反码比特被标记到解码指令。当检测到奇偶校验错误时，指令队列首先检查反pi位是否被设置。如果反pi位被置位，则指令对于错误是中性的，并且不需要设置pi位。预取，分支预测提示和NOP是对错误中立的指令类型。

5. 发明授权

US07353365B2 Implementing check instructions in each thread within a redundant multithreading environments 有权
标题翻译：在冗余多线程环境中的每个线程中实现检查指令
公开(公告)号：US07353365B2
公开(公告)日：2008-04-01
申请号：US10953887
申请日：2004-09-29
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver
IPC分类号： G06F9/318
CPC分类号： G06F11/1494 , G06F11/1695
摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要翻译：描述用于冗余多线程环境中的检查指令的方法和装置。在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。

6. 发明授权

US07243262B2 Incremental checkpointing in a multi-threaded architecture 有权
标题翻译：多线程架构中的增量检查点
公开(公告)号：US07243262B2
公开(公告)日：2007-07-10
申请号：US10651376
申请日：2003-08-29
申请人： Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
发明人： Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F11/366 , G06F9/3851 , G06F9/3863 , G06F11/1494 , G06F11/1629
摘要： A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
摘要翻译：处理器执行相应的指令线程作为前导线程和尾随线程。对于所选择的指令，与指令的执行相对应的处理器状态被保存在历史缓冲器中。这是在将所选指令的结果写入目的寄存器之前进行的。在前导线程中执行所选择的指令的结果与执行拖尾线程中所选指令的结果进行比较。如果比较指示故障，则恢复与先前指令相对应的处理器状态。来自历史缓冲区的数据用于执行恢复。

7. 发明授权

US07444497B2 Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support 有权
标题翻译：使用推测内存支持，在冗余多线程系统中管理外部内存更新以进行故障检测
公开(公告)号：US07444497B2
公开(公告)日：2008-10-28
申请号：US10750039
申请日：2003-12-30
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer , Christopher T. Weaver
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer , Christopher T. Weaver
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F11/1494 , G06F11/1497
摘要： A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
摘要翻译：公开了一种多线程体系结构，用于管理使用推测性内存支持的冗余多线程系统中的故障检测的外部存储器更新。特别地，一种方法通过使用推测性存储器支持将冗余线程从外部更新隔离，从而在SRT处理器上提供负载值的输入复制。因此，该方法避免了专用结构提供输入复制的需要。

8. 发明授权

US07308607B2 Periodic checkpointing in a redundantly multi-threaded architecture 有权
标题翻译：冗余多线程架构中的定期检查点
公开(公告)号：US07308607B2
公开(公告)日：2007-12-11
申请号：US10651388
申请日：2003-08-29
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F9/3851 , G06F9/3863
摘要： A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.
摘要翻译：具有一个或多个检查器电路的多线程架构，其操作于在复制范围之外发送数据的存储操作。用于检查复制领域的输出的故障检测机制在执行时间结束时重新用于检查点。

9. 发明授权

US07587663B2 Fault detection using redundant virtual machines 有权
标题翻译：使用冗余虚拟机进行故障检测
公开(公告)号：US07587663B2
公开(公告)日：2009-09-08
申请号：US11439485
申请日：2006-05-22
申请人： Steven K. Reinhardt , Shubhendu S. Mukherjee
发明人： Steven K. Reinhardt , Shubhendu S. Mukherjee
IPC分类号： G06F11/14
CPC分类号： G06F11/1484 , G06F11/16
摘要： A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.
摘要翻译：一种检测计算机系统中的错误的技术。更具体地，本发明的至少一个实施例涉及使用冗余虚拟机和比较逻辑来检测在计算机系统中的输入/输出（I / O）操作中发生的错误。

10. 发明授权

US06598122B2 Active load address buffer 有权
标题翻译：活动负载地址缓冲区
公开(公告)号：US06598122B2
公开(公告)日：2003-07-22
申请号：US09839621
申请日：2001-04-19
申请人： Shubhendu S. Mukherjee , Steven K. Reinhardt
发明人： Shubhendu S. Mukherjee , Steven K. Reinhardt
IPC分类号： G06F1208
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F11/141 , G06F11/1497
摘要： A redundantly threaded processor is disclosed having an Active Load Address Buffer (“ALAB”) that ensures efficient replication of data values retrieved from the data cache. In one embodiment, the processor comprises a data cache, instruction execution circuitry, and an ALAB. The instruction execution circuitry executes instructions in two or more redundant threads. The threads include at least one load instruction that causes the instruction execution circuitry to retrieve data from the data cache. The ALAB includes entries that are associated with data values that a leading thread has retrieved. The entries include a counter field that is incremented when the instruction execution circuitry retrieves the associated data value for the leading thread, and that is decremented with the associated data value is retrieved for the trailing thread. The entries preferably also include an invalidation field which may be set to prevent further incrementing of the counter field.
摘要翻译：公开了一种冗余线程处理器，其具有确保从数据高速缓存检索的数据值的有效复制的活动负载地址缓冲器（“ALAB”）。在一个实施例中，处理器包括数据高速缓存，指令执行电路和ALAB。指令执行电路在两个或多个冗余线程中执行指令。线程包括使指令执行电路从数据高速缓存中检索数据的至少一个加载指令。 ALAB包括与前导线程已检索的数据值相关联的条目。这些条目包括一个计数器字段，当指令执行电路检索前导线程的相关联的数据值时递增计数器字段，并且为后续线程检索关联的数据值而递减的计数器字段。条目优选地还包括无效字段，其可以被设置为防止计数器字段的进一步递增。

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