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21. 发明授权

US09467047B2 DC-DC converter, power source circuit, and semiconductor device 有权
标题翻译： DC-DC转换器，电源电路和半导体器件
公开(公告)号：US09467047B2
公开(公告)日：2016-10-11
申请号：US13477588
申请日：2012-05-22
申请人： Takuro Ohmaru
发明人： Takuro Ohmaru
IPC分类号： G05F1/575 , H02M3/156 , H02M3/157 , H02M3/158
CPC分类号： H02M3/157
摘要： A DC-DC converter includes a control circuit, a switching element, and a constant-voltage generation portion which generates an output voltage on the basis of an input voltage supplied through the switching element. The control circuit includes AD converters which convert the input voltage and the output voltage, a signal processing circuit, a pulse modulation circuit, and a power supply control circuit which controls supply of a power supply voltage to the signal processing circuit in accordance with digital values of the input voltage and the output voltage. The signal processing circuit determines the duty ratio in accordance with the digital value of the output voltage, and the pulse modulation circuit controls the switching element. The signal processing circuit includes a memory device including a memory element, a capacitor for storing data of the memory element, and a transistor for controlling charge in the capacitor. The transistor includes an oxide semiconductor.
摘要翻译： DC-DC转换器包括控制电路，开关元件和恒定电压产生部分，其根据通过开关元件提供的输入电压产生输出电压。控制电路包括转换输入电压和输出电压的AD转换器，信号处理电路，脉冲调制电路和电源控制电路，其根据数字值控制向信号处理电路的电源电压供应的输入电压和输出电压。信号处理电路根据输出电压的数字值来确定占空比，并且脉冲调制电路控制开关元件。信号处理电路包括存储器件，其包括存储元件，用于存储存储元件的数据的电容器和用于控制电容器中的电荷的晶体管。晶体管包括氧化物半导体。

22. 发明授权

US08825943B2 Semiconductor device and driving method the same 有权
标题翻译：半导体器件和驱动方法相同
公开(公告)号：US08825943B2
公开(公告)日：2014-09-02
申请号：US12872254
申请日：2010-08-31
申请人： Masato Ishii , Yasuyuki Takahashi , Takuro Ohmaru , Hidetomo Kobayashi , Yutaka Shionoiri
发明人： Masato Ishii , Yasuyuki Takahashi , Takuro Ohmaru , Hidetomo Kobayashi , Yutaka Shionoiri
IPC分类号： G06F12/02
CPC分类号： G06F12/1433 , G06F2212/178
摘要： In a semiconductor device including a control circuit and a memory, the memory includes at least a sector for preventing additional writing and an information sector. When data for preventing additional writing is written to the sector for preventing additional writing and information is written to the information sector which is electrically connected to the sector for preventing additional writing, additional writing to the information sector is impossible.
摘要翻译：在包括控制电路和存储器的半导体器件中，存储器至少包括用于防止额外写入的扇区和信息扇区。当防止额外写入的数据被写入扇区以防止额外写入时，信息被写入与扇区电连接以防止额外写入的信息扇区，对信息扇区的额外写入是不可能的。

23. 发明申请

US20120306533A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120306533A1
公开(公告)日：2012-12-06
申请号：US13481148
申请日：2012-05-25
申请人： Takuro Ohmaru
发明人： Takuro Ohmaru
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/0013 , H01L25/00 , H01L2924/0002 , H03K19/177 , H03K19/17744 , H01L2924/00
摘要： A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.
摘要翻译：可编程模拟设备和模拟设备即使在供电电源中断并且功耗较低时也能保留数据。在半导体器件中，第一至第四晶体管用作包括模拟元件的单元的开关，并且单元的输出通过模拟元件通过模拟元件在导通状态，非导通状态和导通状态之间切换，控制第一晶体管和第二晶体管连接的第一节点的电位以及第三晶体管和第四晶体管连接的第二节点的电位。

24. 发明申请

US20120250397A1 SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20120250397A1
公开(公告)日：2012-10-04
申请号：US13429668
申请日：2012-03-26
申请人： Takuro Ohmaru
发明人： Takuro Ohmaru
IPC分类号： G11C11/24
CPC分类号： G11C14/0018 , G11C11/24 , G11C11/404 , G11C16/0416 , H01L21/84 , H01L27/0688 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/1156 , H01L27/1203 , H01L29/7869
摘要： The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output.
摘要翻译：存储装置包括易失性第一存储器电路和非易失性第二存储器电路，其包括其通道形成在氧化物半导体层中的晶体管。在高频驱动的情况下，在施加电源电压的期间，数据信号被输入到第一存储电路并从第一存储电路输出，并且在供给源电压的期间的一部分期间的源电压停止，数据信号被输入到第二存储电路。在低频驱动的情况下，在施加电源电压的期间，将数据信号输入到第二存储电路，输入到第二存储电路的数据信号输入到第一存储电路，数据信号输出到第一存储器电路的输入。

25. 发明申请

US20120170355A1 STORAGE ELEMENT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT 有权
标题翻译：存储元件，存储器件和信号处理电路
公开(公告)号：US20120170355A1
公开(公告)日：2012-07-05
申请号：US13341412
申请日：2011-12-30
申请人： Takuro Ohmaru , Masami Endo
发明人： Takuro Ohmaru , Masami Endo
IPC分类号： G11C11/24
CPC分类号： H01L27/1052 , G06F1/3275 , G11C11/24 , G11C14/0009 , G11C19/184 , H01L23/5226 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10897 , H01L28/20 , H01L28/40 , H01L29/24 , H01L29/26 , H01L29/7869 , Y02D10/13 , Y02D10/14
摘要： A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.
摘要翻译：提供能够抑制功耗的信号处理电路。在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。因此，可以准确地读取原始信号。

26. 发明授权

US10079053B2 Memory element and memory device 有权
公开(公告)号：US10079053B2
公开(公告)日：2018-09-18
申请号：US13444177
申请日：2012-04-11
申请人： Takuro Ohmaru , Yukio Maehashi
发明人： Takuro Ohmaru , Yukio Maehashi
IPC分类号： G11C14/00 , G11C11/412
CPC分类号： G11C11/412 , G11C14/0054
摘要： An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.

27. 发明授权

US08817527B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08817527B2
公开(公告)日：2014-08-26
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/00 , G06F12/08
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

28. 发明授权

US08773906B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US08773906B2
公开(公告)日：2014-07-08
申请号：US13356749
申请日：2012-01-24
申请人： Takuro Ohmaru
发明人： Takuro Ohmaru
IPC分类号： G11C14/00 , G11C5/14 , G11C11/34 , G11C11/41 , H01L29/788 , H01L29/792
CPC分类号： G11C14/0018 , G11C5/14 , G11C11/34 , G11C11/41 , G11C14/00 , G11C14/0063 , H01L21/8258 , H01L27/0688 , H01L27/1156 , H01L27/1207 , H01L29/788 , H01L29/792
摘要： The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.
摘要翻译：本发明提供了一种存储电路，其中在不提供电力的情况下，已经保存在与易失性存储器相对应的存储器部分中的数据信号可以被保存在与非易失性存储器相对应的存储器部分中的电容器中。在非易失性存储器部分中，其沟道形成在氧化物半导体层中的晶体管允许信号被长时间保持在电容器中。因此，即使在电源停止的情况下，存储电路也可以保持逻辑状态（数据信号）。施加到其沟道形成在氧化物半导体层中的晶体管的栅极的电位由设置在用于承载电源电位的布线和晶体管的栅极之间的升压电路升高，允许数据信号被保持为一个电源电位无故障。

29. 发明授权

US08705267B2 Integrated circuit, method for driving the same, and semiconductor device 有权
公开(公告)号：US08705267B2
公开(公告)日：2014-04-22
申请号：US13307060
申请日：2011-11-30
申请人： Masami Endo , Takuro Ohmaru
发明人： Masami Endo , Takuro Ohmaru
IPC分类号： G11C11/24 , G11C11/00 , G11C11/34 , G11C8/00
CPC分类号： H03K3/356008 , H03K3/012 , H03K21/023 , H03K21/403
摘要： An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

30. 发明授权

US08575985B2 Storage element, storage device, and signal processing circuit 有权
公开(公告)号：US08575985B2
公开(公告)日：2013-11-05
申请号：US13341412
申请日：2011-12-30
申请人： Takuro Ohmaru , Masami Endo
发明人： Takuro Ohmaru , Masami Endo
IPC分类号： H03K3/356
CPC分类号： H01L27/1052 , G06F1/3275 , G11C11/24 , G11C14/0009 , G11C19/184 , H01L23/5226 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10897 , H01L28/20 , H01L28/40 , H01L29/24 , H01L29/26 , H01L29/7869 , Y02D10/13 , Y02D10/14
摘要： A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

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