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21. 发明授权

US06388920B2 Semiconductor memory device having faulty cells 有权
公开(公告)号：US06388920B2
公开(公告)日：2002-05-14
申请号：US09886133
申请日：2001-06-22
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

22. 发明授权

US06317371B2 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory 有权
标题翻译：具有错误校正单元的存储设备和用于访问和传送存储在非易失性半导体存储器中的数据块的改进布置
公开(公告)号：US06317371B2
公开(公告)日：2001-11-13
申请号：US09824778
申请日：2001-04-04
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

23. 发明授权

US06236601B1 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US06236601B1
公开(公告)日：2001-05-22
申请号：US09477665
申请日：2000-01-05
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C700
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.
摘要翻译：一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

24. 发明申请

US20100257313A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100257313A1
公开(公告)日：2010-10-07
申请号：US12303110
申请日：2007-05-16
申请人： Hirotaka Nishizawa , Junichiro Osako , Minoru Shinohara , Tamaki Wada , Kunihirio Katayama , Shigemasa Shiota
发明人： Hirotaka Nishizawa , Junichiro Osako , Minoru Shinohara , Tamaki Wada , Kunihirio Katayama , Shigemasa Shiota
IPC分类号： G06F12/00 , G06F1/32 , G06F1/26
CPC分类号： G06K19/077 , G06K19/0719 , G06K19/072
摘要： A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.
摘要翻译：半导体器件具有通过第二微型计算机（113）的控制可选择的操作模式。在第一模式中，分别响应来自存储卡接口终端的存储卡命令的存储器控制器（105）的操作和来自IC卡接口终端的响应IC卡命令的第一微计算机（106）的操作执行。在第二模式中，第一微型计算机响应于来自IC卡接口终端的IC卡命令而工作。在第三模式中，存储器控制器和第一微型计算机响应于来自IC卡接口终端的未定义的IC卡命令来操作。在第四模式中，存储器控制器和第一微型计算机响应来自存储卡接口终端的存储卡命令而操作。提高具有IC卡功能和存储卡功能的半导体器件的便利性。

25. 发明申请

US20100054069A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20100054069A1
公开(公告)日：2010-03-04
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

26. 发明申请

US20080229164A1 MEMORY CARD AND MEMORY CONTROLLER 失效
标题翻译：内存卡和内存控制器
公开(公告)号：US20080229164A1
公开(公告)日：2008-09-18
申请号：US12125042
申请日：2008-05-21
申请人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota , Yasuhiro Nakamura
发明人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota , Yasuhiro Nakamura
IPC分类号： G11C29/00
CPC分类号： G06F11/1068
摘要： A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.
摘要翻译：存储卡包括非易失性存储器，用于控制存储卡的操作的存储器控制器。存储器控制器能够根据预定协议向外部提供接口，并且以规定的时间间隔或在电力供应连接的定时执行存储器信息的错误检测和校正，而不依赖于读出存储器信息到外部访问请求。因此，无需主机装置从存储卡的非易失性存储器中读出存储器信息，可以提高非易失性存储器中的数据保持的可靠性。

27. 发明申请

US20080022188A1 MEMORY CARD AND MEMORY CONTROLLER 有权
标题翻译：内存卡和内存控制器
公开(公告)号：US20080022188A1
公开(公告)日：2008-01-24
申请号：US11861190
申请日：2007-09-25
申请人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
发明人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译：存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

28. 发明申请

US20070101237A1 Memory card and memory controller 有权
标题翻译：存储卡和存储控制器
公开(公告)号：US20070101237A1
公开(公告)日：2007-05-03
申请号：US11504016
申请日：2006-08-15
申请人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
发明人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译：存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

29. 发明授权

US07197613B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07197613B2
公开(公告)日：2007-03-27
申请号：US10721086
申请日：2003-11-26
申请人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
发明人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G06F12/12
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.
摘要翻译：旨在检测，通知和保存半导体存储器中的异常区域，大大提高可靠性。提供给存储卡的半导体存储器的内部包括用户区域，替换区域，区域替换信息存储区域和管理区域。半导体存储器的内部包括用户区域，替代区域和管理区域。用户区域是用户可以使用的数据区域。当用户区域发生错误时，替换区域被替换。区域替换信息存储区域存储区域替换区域信息。管理区域存储替换信息。信息处理部分按如下两个级别执行替换。当检测到指示半导体存储器区域中的故障症状的操作时，信息处理部件在存储卡的空闲状态期间执行区域替换。当检测到区域中的故障操作时，信息处理部分立即进行区域替换。

30. 发明申请

US20070038901A1 Nonvolatile memory system 失效
标题翻译：非易失性存储器系统
公开(公告)号：US20070038901A1
公开(公告)日：2007-02-15
申请号：US11583156
申请日：2006-10-19
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G06F11/00
CPC分类号： G11C16/349
摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
摘要翻译：提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

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