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21. 发明授权

US5179303A Signal delay apparatus employing a phase locked loop 失效
标题翻译：采用锁相环的信号延迟装置
公开(公告)号：US5179303A
公开(公告)日：1993-01-12
申请号：US913659
申请日：1992-07-16
申请人： Shawn Searles , Richard G. Kusyk
发明人： Shawn Searles , Richard G. Kusyk
IPC分类号： H03K5/00 , H03K5/13 , H03K5/15 , H03L7/081 , H03L7/089
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/133 , H03K5/1504 , H03L7/0812 , H03L7/0895 , H03K2005/00104 , H03K2005/00208 , H03K2005/00228 , H03K2005/00286 , H03L2207/14
摘要： An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop. A harmonic lock detector connected to a plurality of clock phase taps from the delay line detects harmonic lock conditions for second through tenth harmonics, resetting the delay lock loop in the event of harmonic lock.
摘要翻译：提供一种用于在集成电路内以固定量延迟数字数据信号的装置。延迟锁定环包括自适应延迟线，相位检测器和积分器。积分器根据参考时钟信号phi 0和延迟时钟信号phi的相对相位，提供用于控制延迟线的控制信号cp，cn。延迟线包括多个延迟单元。通过保持相位关系phi n = phi 0 + 360°一个时钟周期，Tc提供延迟线延迟。因此，每个延迟单元提供Tc / n延迟。通过在芯片上的其他位置的信号路径中放置相同的单元，可以引入由延迟锁定环控制的固定延迟。从延迟线连接到多个时钟相位抽头的谐波锁定检测器检测第二到十次谐波的谐波锁定条件，在谐波锁定的情况下复位延迟锁定环路。

22. 发明授权

US5146121A Signal delay apparatus employing a phase locked loop 失效
标题翻译：采用锁相环的信号延迟装置
公开(公告)号：US5146121A
公开(公告)日：1992-09-08
申请号：US782353
申请日：1991-10-24
申请人： Shawn Searles , Richard G. Kusyk
发明人： Shawn Searles , Richard G. Kusyk
IPC分类号： H03K5/00 , H03K5/13 , H03K5/15 , H03L7/081 , H03L7/089
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/133 , H03K5/1504 , H03L7/0812 , H03L7/0895 , H03K2005/00104 , H03K2005/00208 , H03K2005/00228 , H03K2005/00286 , H03L2207/14 , Y10T307/565
摘要： An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c /n delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop.
摘要翻译：提供一种用于在集成电路内以固定量延迟数字数据信号的装置。延迟锁定环包括自适应延迟线，相位检测器和积分器。积分器根据参考时钟信号phi 0和延迟时钟信号phi的相对相位，提供用于控制延迟线的控制信号cp，cn。延迟线包括多个延迟单元。通过保持相位关系phi n = phi 0 + 360°一个时钟周期，Tc提供延迟线延迟。因此，每个延迟单元提供Tc / n延迟。通过在芯片上的其他位置的信号路径中放置相同的单元，可以引入由延迟锁定环控制的固定延迟。

23. 发明授权

US08638145B2 Method for locking a delay locked loop 有权
标题翻译：锁定延迟锁定环路的方法
公开(公告)号：US08638145B2
公开(公告)日：2014-01-28
申请号：US13529671
申请日：2012-06-21
申请人： Shawn Searles
发明人： Shawn Searles
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0812
摘要： A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.
摘要翻译：一种用于将延迟线同步到参考时钟的方法和装置包括：延迟线，其基于参考时钟接收时钟输入信号，并根据控制调整输出延迟边沿信号。喷射器接收参考时钟的第一上升沿并且响应于第一触发，将时钟输入信号发送到延迟线。同步器确定上升沿已经通过延迟线，并且作为响应，向喷射器发送第二触发以将时钟输入信号的下一个单个下降沿发送到延迟线。电荷泵确定延迟边缘信号和从喷射器发送的参考边沿信号之间的定时差。电荷泵将控制信号发送到延迟线，以根据定时差来调整延迟线的延迟设置。

24. 发明授权

US08607104B2 Memory diagnostics system and method with hardware-based read/write patterns 有权
标题翻译：内存诊断系统和基于硬件读/写模式的方法
公开(公告)号：US08607104B2
公开(公告)日：2013-12-10
申请号：US12972977
申请日：2010-12-20
申请人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
发明人： Hanwoo Cho , Tahsin Askar , Philip E. Madrid , Guhan Krishnan , Brian W. Amick , Shawn Searles , Ryan J. Hensley
IPC分类号： G06F11/00
CPC分类号： G11C29/1201 , G11C29/022
摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.
摘要翻译：一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。测试控制逻辑被配置为在连续命令之间产生间隙。配置环回连接将写入数据从写入路径路由到读取路径。数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成地址/命令环回状态输出。

25. 发明授权

US08542068B2 Oscillator with highly-adjustable bang-bang control 有权
标题翻译：振荡器具有高度可调的爆炸控制
公开(公告)号：US08542068B2
公开(公告)日：2013-09-24
申请号：US13332990
申请日：2011-12-21
申请人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
发明人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
IPC分类号： H03L7/00
CPC分类号： H03L7/0807 , H03K3/0322 , H03L7/087 , H03L7/0995
摘要： A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.
摘要翻译：器件可以包括基于第一和第二控制信号产生时钟信号的振荡器。振荡器可以包括第一缓冲级，第二缓冲级。第一缓冲级可以输出基于第二缓冲级和第一控制信号的输出的第一信号。第二缓冲级可以输出时钟信号。时钟信号可以基于第一信号和第二控制信号。

26. 发明申请

US20130169329A1 METHOD FOR LOCKING A DELAY LOCKED LOOP 有权
标题翻译：用于锁定延迟锁定环的方法
公开(公告)号：US20130169329A1
公开(公告)日：2013-07-04
申请号：US13529671
申请日：2012-06-21
申请人： Shawn Searles
发明人： Shawn Searles
IPC分类号： H03L7/08
CPC分类号： H03L7/10 , H03L7/0812
摘要： A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.
摘要翻译：一种用于将延迟线同步到参考时钟的方法和装置包括：延迟线，其基于参考时钟接收时钟输入信号，并根据控制调整输出延迟边沿信号。喷射器接收参考时钟的第一上升沿并且响应于第一触发，将时钟输入信号发送到延迟线。同步器确定上升沿已经通过延迟线，并且作为响应，向喷射器发送第二触发以将时钟输入信号的下一个单个下降沿发送到延迟线。电荷泵确定延迟边缘信号和从喷射器发送的参考边沿信号之间的定时差。电荷泵将控制信号发送到延迟线，以根据定时差来调整延迟线的延迟设置。

27. 发明申请

US20120284576A1 HARDWARE STIMULUS ENGINE FOR MEMORY RECEIVE AND TRANSMIT SIGNALS 审中-公开
标题翻译：用于记忆接收和发送信号的硬件激光发动机
公开(公告)号：US20120284576A1
公开(公告)日：2012-11-08
申请号：US13102975
申请日：2011-05-06
申请人： Oswin E. Housty , Harold H. Bautista , Shawn Searles
发明人： Oswin E. Housty , Harold H. Bautista , Shawn Searles
IPC分类号： G06F11/267 , G06F12/00
CPC分类号： G06F13/1694 , G06F13/1689 , G11C29/023 , G11C29/028 , G11C29/50012
摘要： Techniques and structures are disclosed in which memory training for DDR or other memory can be performed more rapidly. A memory controller is configured so that one or more memory parameters (e.g., timing delay) can be determined for one or more hardware elements such as delay locked loops (DLLs). Training may be performed without intermediation by (or reporting of results to) a system BIOS. Thus, training may be performed fully in hardware. Voltage training techniques are also disclosed.
摘要翻译：公开了可以更快地执行用于DDR或其他存储器的存储器训练的技术和结构。存储器控制器被配置为使得可以为一个或多个硬件元件（例如延迟锁定环（DLL））确定一个或多个存储器参数（例如，定时延迟）。培训可以不通过系统BIOS的（或报告结果）中介来执行。因此，可以在硬件中完全进行训练。还公开了电压训练技术。

28. 发明授权

US07929361B2 Circuit using a shared delay locked loop (DLL) and method therefor 有权
标题翻译：电路使用共享延迟锁定环（DLL）及其方法
公开(公告)号：US07929361B2
公开(公告)日：2011-04-19
申请号：US12059613
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.
摘要翻译：收发器（222）包括接收电路（320），发射电路（340），共享延迟锁定环（DLL）（360）和控制器（210）。接收电路（320）具有耦合到外部数据终端的第一输入，耦合到外部数据选通端的第二输入和耦合到内部数据终端的输出。发射电路（340）具有耦合到内部数据终端的第一输入端，用于接收内部时钟信号的第二输入端，耦合到外部数据端子的第一输出端和耦合到外部数据选通端子的第二输出端。控制器（210）使得共享DLL（360）能够在接收周期期间由接收电路（320）使用，并且使得共享DLL（360）能够在发送周期期间由发送电路（340）使用。

29. 发明申请

US20090296501A1 Method and Apparatus for Implementing Write Levelization in Memory Subsystems 有权
标题翻译：用于在存储器子系统中实现写等级化的方法和装置
公开(公告)号：US20090296501A1
公开(公告)日：2009-12-03
申请号：US12127059
申请日：2008-05-27
申请人： Shawn Searles
发明人： Shawn Searles
IPC分类号： G11C7/22
CPC分类号： G06F13/1689
摘要： Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine configured to receive an error signal from a corresponding memory device, wherein the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.
摘要翻译：公开了用于对准时钟信号和一组选通信号的方法和装置。在一个实施例中，存储器控制器包括被配置为产生时钟信号的时钟发生器和被配置为产生每个选通信号的相应选通信号发生器。存储器控制器还包括相位恢复引擎，其被配置为从相应的存储器件接收错误信号，其中，误差信号传送指示针对多个周期中的每个周期的选通信号相对于时钟信号的对准的错误指示选通信号。相位恢复引擎包括一个累加器，被配置为保持取决于选通信号的多个周期的错误指示的累加值。选通信号发生器被配置为根据积累值来控制与产生选通信号相关联的延迟。

30. 发明申请

US20140049292A1 INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY 审中-公开
标题翻译：具有中型独立信号接口的集成电路封装与连接器总成相连
公开(公告)号：US20140049292A1
公开(公告)日：2014-02-20
申请号：US13588704
申请日：2012-08-17
申请人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
发明人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
IPC分类号： H01R12/70 , G02B6/36 , H03K5/01
CPC分类号： G02B6/43 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/014 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.
摘要翻译：集成电路（IC）封装包括设置在IC封装的第一表面处的电触点，实现电信令接口的集成电路以及可在IC封装的第二表面处接近的连接器组件。连接器组件将机械地连接到另一个连接器组件，并且包括电耦合到电信令接口的接触端子。连接器组件可以被配置为提供与另一连接器组件的摩擦联接，以允许另一连接器组件可移除地附接。一种系统包括IC封装和具有机械连接到IC封装的连接器组件的连接器组件的外部收发器模块。电信令接口根据一种信号格式与外部收发器模块进行信号通信，而外部收发器模块根据另一信号格式通过传输介质进行信令传输。

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