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21. 发明授权

US08539159B2 Dirty cache line write back policy based on stack size trend information 有权
标题翻译：基于堆栈大小趋势信息的脏缓存行回写策略
公开(公告)号：US08539159B2
公开(公告)日：2013-09-17
申请号：US10631185
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F2212/502
摘要： Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.
摘要翻译：公开了用于管理存储器回写的方法和装置。在一些实施例中，该方法可以包括检查在存储器中存在的堆栈上操作的当前和未来指令，从指令确定堆栈趋势信息，以及利用趋势信息来减少存储器的各个级别之间的数据流量。当堆叠数据被写入第一级存储器中的高速缓存行时，如果未来的指令指示需要额外的高速缓存行用于堆栈内的后续写入操作，则高速缓存行可以被写回到第二级存储器。然而，如果未来的指令指示不需要额外的高速缓存行用于堆栈内的后续写入操作，则第一级存储器可以避免写回高速缓存行并且还可以将其标记为脏。

22. 发明授权

US07941790B2 Data processing apparatus, system and method 有权
标题翻译：数据处理装置，系统及方法
公开(公告)号：US07941790B2
公开(公告)日：2011-05-10
申请号：US10003570
申请日：2001-10-24
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Gerard Chauvel , Dominique D'Inverno , Teresa Higuera , Valerie Issarny , Serge Lasserre , Frederic Parain , Jean-Paul Routeau
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Gerard Chauvel , Dominique D'Inverno , Teresa Higuera , Valerie Issarny , Serge Lasserre , Frederic Parain , Jean-Paul Routeau
IPC分类号： G06F9/45
CPC分类号： G06F8/447 , G06F8/47
摘要： A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.
摘要翻译：一种用于产生用于将高级代码转换为多个目标处理器之一的指令的程序代码的方法包括首先确定与目标处理器相对应的期望的程序代码特性。然后，根据所述期望的程序代码特征从多个可用的程序代码模块中选择一个或多个预定义的程序代码模块，以及生成用于将所述目标处理器从所述选定的一个或多个预定程序转换成指令的程序代码代码模块优选地，该方法包括根据所述期望的程序代码特征从多个程序代码模块形成聚集的程序代码。

23. 发明授权

US07840782B2 Mixed stack-based RISC processor 有权
标题翻译：基于混合堆栈的RISC处理器
公开(公告)号：US07840782B2
公开(公告)日：2010-11-23
申请号：US10631308
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502 , Y02D10/13
摘要： A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.
摘要翻译：尽管在本公开的范围内不需要代码加速，处理器（例如，协处理器）以加速基于堆栈的指令集的执行的方式执行基于堆栈的指令集和另一指令。根据本发明的至少一些实施例，处理器可以包括可用于至少基于堆栈的指令集，耦合到和管理堆栈的逻辑的多入栈，以及耦合到逻辑和可寻址的多个寄存器通过提供基于寄存器和基于存储器的操作的第二指令集。

24. 发明授权

US07634643B2 Stack register reference control bit in source operand of instruction 有权
标题翻译：指令源操作数中的堆栈寄存器参考控制位
公开(公告)号：US07634643B2
公开(公告)日：2009-12-15
申请号：US10632214
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F9/00
CPC分类号： G06F9/30134 , G06F9/30072 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in the instruction. Based on the outcome of test, the subsequent instruction is executed or skipped. Further, the instruction includes at least one bit that specifies how the test is to be performed. The bit may specify that the immediate value is to be compared to the register value, or that the immediate value is used to mask the register value and the masked register value has one or more of its bits tested.
摘要翻译：本文公开的处理器可以执行包括立即值和对处理器可访问的寄存器的引用的指令。该指令使处理器使用指令中引用的立即值和寄存器的内容来执行测试。根据测试结果，后续指令被执行或跳过。此外，指令包括指定如何执行测试的至少一个位。该位可以指定立即值与寄存器值进行比较，或者立即值用于屏蔽寄存器值，并且屏蔽寄存器值具有测试的一个或多个位。

25. 发明授权

US07509391B1 Unified memory management system for multi processor heterogeneous architecture 有权
标题翻译：用于多处理器异构架构的统一内存管理系统
公开(公告)号：US07509391B1
公开(公告)日：2009-03-24
申请号：US09448569
申请日：1999-11-23
申请人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques d'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques d'Inverno
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F12/1027 , G06F12/1081
摘要： A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual address space mapped to an external shared memory (20). The MMUs (19, 32) may perform the translation between a virtual address and the physical address associated with the external shared memory (20). Access to the shared memory (20) is controlled using a unified memory management system.
摘要翻译：多处理器系统8包括多个处理设备，包括DSP（10），处理器单元（MPU）（21），协处理器（30）和DMA通道（31）。一些设备可以包括允许设备（10,21,30,31）与映射到外部共享存储器（20）的大的虚拟地址空间一起工作的内部MMU（19,32）。 MMU（19,32）可以执行虚拟地址与与外部共享存储器（20）相关联的物理地址之间的转换。使用统一的存储器管理系统来控制对共享存储器（20）的访问。

26. 发明授权

US07360060B2 Using IMPDEP2 for system commands related to Java accelerator hardware 有权
标题翻译：使用IMPDEP2与Java加速器硬件相关的系统命令
公开(公告)号：US07360060B2
公开(公告)日：2008-04-15
申请号：US10632069
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30149 , G06F9/30174 , G06F9/30185 , G06F9/30189 , G06F9/382 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines the mode of operation for the decode logic for subsequent instructions. In particular, the decode logic operating in a current mode concurrently with the pre-decoder detecting a predetermined prefix, which indicates a subsequent instruction is a system command. Upon detecting this predetermined prefix, the decoder decodes the system command accordingly.
摘要翻译：包括解码器的处理器（例如，协处理器），其适于在第一模式中解码来自第一指令集的指令和在第二模式中的第二指令集。耦合到解码器并且与解码器并行操作的预解码器确定用于随后指令的解码逻辑的操作模式。特别地，与预解码器同时检测预定前缀的当前模式的解码逻辑，其指示后续指令是系统命令。在检测到该预定前缀时，解码器相应地解码系统命令。

27. 发明授权

US06789172B2 Cache and DMA with a global valid bit 有权
标题翻译：具有全局有效位的缓存和DMA
公开(公告)号：US06789172B2
公开(公告)日：2004-09-07
申请号：US09932794
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0835 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to indicate if any segment of the multiple segments holds valid data. Block circuitry is operable to transfer data from a pre-selected region of the secondary memory to a particular segment of the plurality of segments and to assert the global valid bit at the completion of a block transfer. Direct memory access (DMA) circuitry is connected to the memory cache for transferring data between the memory cache and a selectable region of a secondary memory and is also operable to assert the global valid bit at the completion of a DMA block transfer.
摘要翻译：数字系统具有至少一个具有相关联的多段高速缓冲存储器电路的处理器。单个全局有效性电路（VIG）连接到存储器电路并且可操作以指示多个段的任何段是否保存有效数据。块电路可操作以将数据从辅助存储器的预选区域传送到多个段的特定段，并且在块传送完成时断言全局有效位。直接存储器访问（DMA）电路连接到存储器高速缓存，用于在存储器高速缓存和辅助存储器的可选择区域之间传送数据，并且还可用于在DMA块传送完成时断言全局有效位。

28. 发明授权

US07386671B2 Smart cache 有权
标题翻译：智能缓存
公开(公告)号：US07386671B2
公开(公告)日：2008-06-10
申请号：US10891821
申请日：2004-07-14
申请人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0864
摘要： A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译：用于处理设备的高速缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM组高速缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。寄存器（32）定义主存储器（20）的连续块的起始地址。与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上地址被加载到寄存器（32）中。由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。

29. 发明授权

US06851072B2 Fault management and recovery based on task-ID 有权
标题翻译：基于任务ID的故障管理和恢复
公开(公告)号：US06851072B2
公开(公告)日：2005-02-01
申请号：US09932378
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1/20 , G06F1/32 , G06F9/312 , G06F9/50 , G06F11/07 , G06F11/20 , G06F11/34 , G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F11/0715 , G06F11/0772 , G06F11/0793 , G06F11/1666 , G06F11/20 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/24
摘要： In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality of program tasks is executed on the processor (800). The processor requests access to memory in response to executing the tasks (802). Some of these access requests are not directly or not straightforwardly linked with the current program counter (PC); for example, a write transaction going through a write buffer (808). An access error resulting form this type of transaction error is referred to as an imprecise abort. A task-id value is supplied along with the address during a deferred memory access and corresponds to the task-id of the task that initiated the memory access (802). If an error condition that prevents normal completion of the memory transaction is detected (806), then a recovery routine uses the task-id value provided with the memory transaction request to identify which program task requested the transaction (810, 812). The recovery routine can then resolve the problem or kill the identified task.
摘要翻译：根据本发明的第一实施例，提供了一种操作具有处理器和存储器的数字系统的方法。在处理器（800）上执行多个程序任务。响应于执行任务，处理器请求访问存储器（802）。这些访问请求中的一些不直接或不直接与当前的程序计数器（PC）链接; 例如，通过写入缓冲器的写入事务（808）。这种类型的事务错误导致的访问错误被称为不精确中止。任务ID值与延迟存储器访问期间的地址一起提供，并且对应于启动存储器访问的任务的任务ID（802）。如果检测到存储器事务的正常完成的错误条件（806），则恢复例程使用与存储器事务请求一起提供的task-id值来识别请求事务的程序任务（810,812）。然后，恢复例程可以解决问题或者杀死已识别的任务。

30. 发明授权

US06697916B2 Cache with block prefetch and DMA 有权
标题翻译：缓存带块预取和DMA
公开(公告)号：US06697916B2
公开(公告)日：2004-02-24
申请号：US09932650
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1206
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0835 , G06F12/0862 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. Fetch circuitry associated with the memory cache is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert a first valid bit corresponding to the segment when the miss detection circuitry (1610) detects a miss in the segment. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory. The cache can be operated in a first manner such that when a transfer request from the processor requests a first location in the cache memory that does not hold valid data, valid data is transferred (1652) from a pre-selected location in a secondary memory that corresponds directly to the first location. The cache can then be operated in a second manner such that data is transferred (1662) between the first location and a selectable location in the secondary memory, wherein the selected location need not directly correspond to the first location.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以块传输电路（700,702）连接到存储器电路，并且可操作以将数据块（1650）传送到所述多个段的片段（1606）的选定部分与存储器高速缓存相关联的获取电路可操作以将数据从辅助存储器（1650）的预先选择的区域传送到多个段的特定段，并且当对应于该段的第一有效位时未命中检测电路（1610）检测该片段中的未命中，直接存储器访问（DMA）电路（1610）连接到存储器高速缓存，用于在存储器高速缓存和可选区域（1650）之间传送数据第一记忆高速缓存可以以第一方式操作，使得当来自处理器的传送请求请求高速缓冲存储器中不保存有效数据的第一位置时，有效数据从副存储器中的预先选择的位置传送（1652）它直接对应于第一个位置。然后可以以第二方式操作高速缓存，使得数据在辅助存储器中的第一位置和可选位置之间传送（1662），其中所选择的位置不需要直接对应于第一位置。

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