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21. 发明授权

US06209067B1 Computer system controller and method with processor write posting hold off on PCI master memory request 失效
标题翻译：具有处理器写入寄存功能的计算机系统控制器和方法在PCI主存储器请求中保持不变
公开(公告)号：US06209067B1
公开(公告)日：2001-03-27
申请号：US08566514
申请日：1995-12-04
申请人： Michael J. Collins , Michael P. Moriarty , John E. Larson , Jens K. Ramsey
发明人： Michael J. Collins , Michael P. Moriarty , John E. Larson , Jens K. Ramsey
IPC分类号： G06F1336
CPC分类号： G06F13/1605 , G06F12/0831 , G06F13/1642 , G06F13/1694
摘要： A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.
摘要翻译：包括存储器控制器的计算机系统在处理器与外围部件互连（PCI）总线和存储器系统之间提供一系列的队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。在PCI设备可以访问内存之前，必须刷新处理器到PCI写入的写入队列。如果PCI设备请求存储器读取队列不为空，则在刷新写入过帐队列时，强制PCI设备重试该操作。此外，当刷新队列时，防止处理器进一步发布到队列。定时器提供进一步的临时时间，使处理器不被发布以允许足够的时间使PCI主机重试该操作。

22. 发明授权

US06199118B1 System and method for aligning an initial cache line of data read from an input/output device by a central processing unit 有权
标题翻译：用于对准由中央处理单元从输入/输出设备读取的初始高速缓存行数据的系统和方法
公开(公告)号：US06199118B1
公开(公告)日：2001-03-06
申请号：US09135703
申请日：1998-08-18
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F300
CPC分类号： G06F13/404 , G06F12/0879
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i.e., target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order. This ensures the processor controller, and eventually the processor, will read quad words in toggle mode address order, even though the quad words are dispatched from the peripheral device in address-increasing (non-toggle mode) order.
摘要翻译：提供一种具有耦合在CPU总线，PCI总线和/或图形总线之间的总线接口单元的计算机。总线接口单元包括链接到相应总线的控制器，还包括放置在连接各种控制器的地址和数据路径内的多个队列。耦合在处理器本地总线之间的处理器控制器确定从处理器转发的地址是否是用于选择构成高速缓存行的四字组的地址序列中的第一地址。如果地址（即，目标地址）不是该序列中的第一个地址（初始地址），则修改目标地址，使其成为该序列中的初始地址。四个字按顺序接收并放入队列。当四位字被发送到CPU时，它们处于切换顺序。这确保处理器控制器，最终处理器将以切换模式地址顺序读取四个字，即使以寻址增加（非切换模式）顺序从外围设备发送四个字。

23. 发明授权

US5819105A System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device 失效
标题翻译：处理器接口监听第一和第二级缓存的系统与总线主控设备的存储器访问并行
公开(公告)号：US5819105A
公开(公告)日：1998-10-06
申请号：US566556
申请日：1995-12-04
申请人： Michael P. Moriarty , Michael J. Collins , John E. Larson , Gary W. Thome
发明人： Michael P. Moriarty , Michael J. Collins , John E. Larson , Gary W. Thome
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.
摘要翻译：存储器控制器在处理器和PCI总线与存储器系统之间提供一系列的队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当PCI设备执行存储器读取时，处理器缓存和L2高速缓存与存储器读取操作并行地窥探。在窥探操作完成之前，不提供数据。如果窥探操作指示修改的位置，则在向PCI总线提供数据之前执行写回操作。如果数据在存储器和高速缓存之间是一致的，则从存储器向PCI总线提供数据。

24. 发明授权

US5793693A Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation 失效
标题翻译：使用独特的突发计数器电路和异步交错RAM存储区的缓存存储器进行零等待状态操作
公开(公告)号：US5793693A
公开(公告)日：1998-08-11
申请号：US743501
申请日：1996-11-04
申请人： Michael J. Collins , Jeffrey C. Stevens , Guy E. McSwain
发明人： Michael J. Collins , Jeffrey C. Stevens , Guy E. McSwain
IPC分类号： G06F12/08 , G11C13/00
CPC分类号： G06F12/0851 , G06F12/0879
摘要： A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2. Subsequent accesses are controlled by the burst counter in a synchronous fashion that corresponds to a processor specific burst ordering scheme. Due in part to the interleaved nature of the data SRAM, subsequent burst accesses are allotted almost 2 full clock cycles per data access. Thus, the shortest time in which the data SRAM must respond to an access request is the initial one and one-half clock cycles. Slower and less expensive data SRAMs can therefore be used to provide a cache memory capable of zero wait state operation.
摘要翻译：一种利用异步/同步突发计数器电路的高速缓冲存储器系统，其减少了对昂贵的高速数据SRAM的需求以实现零等待状态操作。脉冲串计数器电路充分利用在脉冲串读取期间读取地址在初始总线周期（T1）大约一半的地址总线上存在的事实。与同步现有技术的突发计数器不同，根据本发明的突发计数器电路被配置为一旦存在就将地址转发到异步地址解码器，而不是等待处理器时钟的下一个上升沿。为了访问第一高速缓存行，定时预算因此包括突发读取（T2）的第一个完整时钟周期以及T1的额外的半个时钟周期。额外的时间用于从数据SRAM核心检索数据，以在总线周期T2结束时提供给处理器数据总线。随后的访问由对应于处理器专用突发排序方案的同步方式由突发计数器控制。部分地由于数据SRAM的交错性质，随后的突发存取被分配给每个数据访问几乎2个整个时钟周期。因此，数据SRAM必须响应访问请求的最短时间是初始的一个半个时钟周期。因此，较慢且较便宜的数据SRAM可用于提供能够进行零等待状态操作的高速缓冲存储器。

25. 发明授权

US5781925A Method of preventing cache corruption during microprocessor pipelined burst operations 失效
标题翻译：在微处理器流水线突发操作期间防止高速缓存损坏的方法
公开(公告)号：US5781925A
公开(公告)日：1998-07-14
申请号：US567030
申请日：1995-12-04
申请人： John E. Larson , Jens K. Ramsey , Jeffrey C. Stevens , Michael J. Collins
发明人： John E. Larson , Jens K. Ramsey , Jeffrey C. Stevens , Michael J. Collins
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0879 , G06F12/0859
摘要： In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.
摘要翻译：在实现高速缓冲存储器的微计算机系统中，微处理器可以执行背靠背流水线突发操作，而不会破坏高速缓冲存储器的内部地址。来自处理器的地址选通脉冲被高速缓存存储器控制器阻挡，允许突发操作在第二地址被选通到高速缓存之前从高速缓存存储器完成。

26. 发明授权

US4753889A Analytical method for determining volatiles, solids and solvent extractables 失效
标题翻译：用于测定挥发物，固体和溶剂可萃取物的分析方法
公开(公告)号：US4753889A
公开(公告)日：1988-06-28
申请号：US782072
申请日：1985-09-30
申请人： Michael J. Collins
发明人： Michael J. Collins
IPC分类号： G01N5/04 , G01N22/00 , G01N22/04 , G01N25/14
CPC分类号： G01N5/04 , G01N5/045 , Y10S436/908 , Y10T436/11 , Y10T436/255
摘要： An apparatus and method for quantitatively measuring volatiles, solids and solvent extractables is described which provides rapid and accurate determinations using microwave heating, electronic balance weighing and solvent extracting of solubles. The method involves subjecting a weighed sample to microwave drying for a preselected time, reweighing to obtain the dry weight and determine volatile loss, solvent extracting the dried sample to determine fats, oils and other extractables followed by final measurement of residual solids. The apparatus is preferably automated to sequentially actuate the required weighing, microwave heating, solvent extraction, redrying, reweighing and calculation of the percentages of volatiles, solvent solubles and solids. The apparatus and method are particularly suited for analytical uses in the food and dairy industries.
摘要翻译：描述了一种用于定量测量挥发物，固体和溶剂可萃取物的装置和方法，其使用微波加热，电子平衡称重和可溶物的溶剂萃取来提供快速和准确的测定。该方法包括将称重的样品经微波干燥预选的时间，称重以获得干重并确定挥发性损失，溶剂萃取干燥样品以确定脂肪，油和其它可萃取物，然后最终测量残留固体。该装置优选是自动化的，以顺序地启动挥发物，溶剂可溶物和固体的所需称量，微波加热，溶剂萃取，重新干燥，称重和计算。该设备和方法特别适用于食品和乳制品行业的分析用途。

27. 发明授权

US4566804A Apparatuses, processes and articles for controllably heating and drying materials by microwave radiation 失效
标题翻译：用于通过微波辐射可控地加热和干燥材料的装置，工艺和制品
公开(公告)号：US4566804A
公开(公告)日：1986-01-28
申请号：US450198
申请日：1982-12-16
申请人： Michael J. Collins , Wyatt P. Hargett, Jr.
发明人： Michael J. Collins , Wyatt P. Hargett, Jr.
IPC分类号： G01N5/04 , G01N22/04 , H05B6/80 , G01N25/00 , G01G23/18
CPC分类号： G01N22/04 , H05B6/80 , G01N5/045 , H05B2206/046
摘要： An apparatus for controllably heating material directly and indirectly by microwave radiation comprises a chamber in which the material to be heated (often to dryness, as for analysis) is placed, a source of microwave radiation for radiating into materials in such chamber for controllably heating such a material, and a support for such material, which support comprises a matrix of microwave radiation-transmissive material and a particulate microwave absorptive material dispersed in such matric material, which microwave absorptive material has a Curie temperature, above which it becomes microwave transmissive, so as thereby to prevent excessive heating of the support and the material thereon which is to be controllably heated, and which matrix material is stable and form-retaining at the Curie temperature of the dispersed material. Preferably the support will be of a silicone rubber or a polyfluoroalkylene polymer matrix, such as polytetrafluoroethylene, and the dispersed material therein will be a ferrite, garnet or mixture thereof. The apparatus may include a turntable for carrying a plurality of supports or it may include an automatic electronic balance, in both of which embodiments of the invention computerized controls and/or readout means may be present. Also within the invention are the described support, and processes for effecting such heating and/or drying, in one of which processes a particulate diluent or dispersant for the sample being treated is employed to prevent overheating thereof.
摘要翻译：用于通过微波辐射直接和间接地可控地加热材料的装置包括其中放置待加热材料（通常为干燥，用于分析）的室，用于辐射到该室中的材料中的微波辐射源，用于可控地加热一种材料和这种材料的支撑件，其支撑包括微波辐射透射材料的基体和分散在这种基质材料中的颗粒状微波吸收材料，该微波吸收材料具有居里温度，在此之上它变成微波可透射的，因此从而防止支撑件及其上可控制加热的材料的过度加热，并且哪种基体材料在分散材料的居里温度下是稳定的并形成保持的。优选地，载体将是硅橡胶或多氟亚烷基聚合物基质如聚四氟乙烯，并且其中的分散材料将是铁氧体，石榴石或其混合物。该装置可以包括用于承载多个支撑件的转盘，或者它可以包括自动电子天平，在本发明的两个实施例中，可以存在计算机控制和/或读出装置。在本发明中还包括所描述的支撑物，以及用于进行这种加热和/或干燥的方法，其中一种方法是使用待处理样品的颗粒状稀释剂或分散剂来防止其过热。

28. 发明申请

US20120255436A1 CONTROL METHOD AND APPARATUS 有权
标题翻译：控制方法和装置
公开(公告)号：US20120255436A1
公开(公告)日：2012-10-11
申请号：US13081808
申请日：2011-04-07
申请人： Michael J. Collins , David F. Suggs , Sadashiv M. Swami , Richard M. Kelly
发明人： Michael J. Collins , David F. Suggs , Sadashiv M. Swami , Richard M. Kelly
IPC分类号： B03C3/34
CPC分类号： B01D53/22 , B01D53/326 , B01D2256/12 , B01D2257/102 , C01B13/0251 , Y02E60/366
摘要： A method and apparatus for controlling the electrical power applied to an electrically driven oxygen separation device having one or more composite membrane elements to separate oxygen from an oxygen containing feed. The composite membrane elements have a resistance increasing during the operation thereof that would act to reduce oxygen output if applied voltage were held constant. In order to increase the time interval for renewing the composite membrane elements, the electrical potential difference is controlled such that the electric current drawn by the elements remains at a substantially constant level by increasing the electrical potential difference as the resistance increases until a predetermined voltage level is reached. Once this level is obtained, the electrical potential difference is maintained at a constant level and the electric current being drawn and the oxygen output is allowed to decay to a predetermined low level after which the element or elements are replaced.
摘要翻译：一种用于控制施加到具有一个或多个复合膜元件的电驱动氧分离装置以从含氧进料分离氧的电功率的方法和装置。复合膜元件在其操作期间具有电阻增加，如果施加的电压保持恒定，其将用于减少氧输出。为了增加更新复合膜元件的时间间隔，控制电位差，使得由元件汲取的电流通过随着电阻增加直到预定的电压电平来增加电位差而保持在基本上恒定的水平到达了。一旦获得该电平，电位差就保持在一个恒定的水平，并且被抽出的电流和氧气输出被允许衰减到一个预定的低电平，之后元件被替换。

29. 发明申请

US20100328604A1 MYOPIA CONTROL OPHTHALMIC LENSES 有权
标题翻译： MYOPIA控制眼镜
公开(公告)号：US20100328604A1
公开(公告)日：2010-12-30
申请号：US12821927
申请日：2010-06-23
申请人： Michael J. Collins , Brett A. Davis , Khaled A. Chehab , Xu Cheng , D. Robert Iskander
发明人： Michael J. Collins , Brett A. Davis , Khaled A. Chehab , Xu Cheng , D. Robert Iskander
IPC分类号： G02C7/04 , G02C7/02 , G02C7/06 , G06F17/10
CPC分类号： G02C7/047 , G02C7/024 , G02C7/028 , G02C7/04 , G02C2202/24
摘要： Lenses are designed using the corneal topography or wavefront measurements of the eye derived by subtracting the optical power of the eye after orthokeratology treatment from the optical power before orthokeratology treatment.
摘要翻译：透镜使用角膜形貌或波前测量设计，通过从角膜曲率治疗前的光学功率减去角膜矫正治疗后眼睛的光学功率而得到。

30. 发明申请

US20100116133A1 OXYGEN SEPARATION ASSEMBLY AND METHOD 审中-公开
标题翻译：氧分离装置和方法
公开(公告)号：US20100116133A1
公开(公告)日：2010-05-13
申请号：US12267801
申请日：2008-11-10
申请人： David M. Reed , David Suggs , Michael J. Collins , Richard Kelly , Gervase M. Christie
发明人： David M. Reed , David Suggs , Michael J. Collins , Richard Kelly , Gervase M. Christie
IPC分类号： B03C3/06
CPC分类号： C01B13/0255 , B01D53/326 , B01D2053/223 , B01D2256/12 , B01D2257/104 , B01D2258/06 , C01B2210/0046
摘要： The present invention provides an electrically driven oxygen separation assembly and method of applying an electrical potential thereto in which one or more tubular membrane elements are provided having an anode layer, a cathode layer, an electrolyte layer and two current collector layers adjacent to and in contact with the anode layer and the cathode layer and situated on the inside and outside of the at least one tubular membrane element. The potential is applied to one of the two current collector layers at two central spaced locations of the at least one tubular membrane element and to the other of the two current collector layers at least at opposite end locations thereof. As a result the electric current flow through the tubular membrane element is divided into two parts flowing between the two central spaced locations and the opposite end locations.
摘要翻译：本发明提供一种电驱动氧分离组件及其电位施加方法，其中提供一个或多个管状膜元件，其中阳极层，阴极层，电解质层和邻近和接触的两个集电器层与阳极层和阴极层并且位于至少一个管状膜元件的内部和外部。在至少一个管状膜元件的两个中心间隔位置处并且至少在两个集电器层中的另一个至少在其相对的端部位置处将电位施加到两个集电器层中的一个。结果，流过管状膜元件的电流被分成在两个中心间隔位置和相对端部位置之间流动的两个部分。

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