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21. 发明授权

US07759745B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07759745B2
公开(公告)日：2010-07-20
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

22. 发明授权

US07683440B2 Semiconductor memory device 有权
公开(公告)号：US07683440B2
公开(公告)日：2010-03-23
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

23. 发明授权

US07482226B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07482226B2
公开(公告)日：2009-01-27
申请号：US11656438
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

24. 发明申请

US20060081188A1 Deposition system 审中-公开
标题翻译：沉积系统
公开(公告)号：US20060081188A1
公开(公告)日：2006-04-20
申请号：US11107819
申请日：2005-04-18
申请人： Hideki Komori , Masao Sumiyoshi , Toshio Tanaka , Miharu Kawashima
发明人： Hideki Komori , Masao Sumiyoshi , Toshio Tanaka , Miharu Kawashima
IPC分类号： C23C16/00
CPC分类号： C23C14/564 , C23C14/26 , C23C14/30
摘要： A vacuum deposition system comprises a vacuum vessel, an evaporation source holder provided in the vacuum vessel for holding an evaporation substance and a holding jig provided in the vacuum vessel for holding a substrate facing the evaporation source. An adhesion-prevention member is provided at outer peripheries of the evaporation source and the holding jig along an inner wall of the vacuum vessel across a region from a position facing a lateral part of the evaporation source holder to a position facing a lateral part of the holding jig. The adhesion-prevention member is spaced apart from the inner wall of the vacuum vessel. The adhesion-prevention member includes members slanted diagonally downward from the central part side toward the inner wall. Thereby, the adhesion-prevention member prevents an evaporant from the evaporation source from adhering to the inner wall of the vacuum vessel.
摘要翻译：真空沉积系统包括真空容器，设置在用于保持蒸发物质的真空容器中的蒸发源保持器和设置在真空容器中用于保持面向蒸发源的基板的保持夹具。在蒸发源和保持夹具的外周沿着真空容器的内壁横跨从面对蒸发源保持器的侧部的位置到面向该蒸发源的侧部的位置的区域设置防粘附构件夹具防粘附构件与真空容器的内壁间隔开。防粘接构件包括从中心部分侧向内壁倾斜向下倾斜的构件。因此，防粘接部件防止蒸发源蒸发剂粘附到真空容器的内壁。

25. 发明授权

US06528390B2 Process for fabricating a non-volatile memory device 有权
公开(公告)号：US06528390B2
公开(公告)日：2003-03-04
申请号：US09798667
申请日：2001-03-02
申请人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
发明人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

26. 发明授权

US06218227B1 Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer 有权
标题翻译：使用多晶硅作为ONO顶层生成MONOS型闪存单元的方法
公开(公告)号：US06218227B1
公开(公告)日：2001-04-17
申请号：US09426239
申请日：1999-10-25
申请人： Steven K. Park , Arvind Halliyal , Hideki Komori
发明人： Steven K. Park , Arvind Halliyal , Hideki Komori
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating an ONO structure for a MONOS type Flash cell includes growing a first silicon oxide layer over a semiconductor substrate. Thereafter, a silicon nitride layer is formed to overlie the first silicon oxide layer, and a polycrystalline silicon layer is deposited to overlie the silicon nitride layer. By utilizing the polycrystalline silicon layer as the top layer of the ONO structure, a resist layer can be cleaned more aggressively than if the top layer of the ONO structure were an oxide layer. A second silicon oxide layer overlies the polycrystalline layer, of the ONO structure. Since the second silicon oxide layer is deposited on top of polycrystalline silicon after the resist material is cleaned, some resist material can remain on the polycrystalline layer without degrading the performance of the MONOS type cell.
摘要翻译：用于制造用于MONOS型闪存单元的ONO结构的工艺包括在半导体衬底上生长第一氧化硅层。此后，形成氮化硅层以覆盖第一氧化硅层，并且沉积多晶硅层以覆盖氮化硅层。通过利用多晶硅层作为ONO结构的顶层，与ONO结构的顶层是氧化物层相比，可以更积极地清洗抗蚀剂层。第二氧化硅层覆盖ONO结构的多晶层。由于在抗蚀剂材料被清洁之后第二氧化硅层沉积在多晶硅的顶部上，所以一些抗蚀剂材料可以保留在多晶层上而不降低MONOS型电池的性能。

27. 发明授权

US06117730A Integrated method by using high temperature oxide for top oxide and periphery gate oxide 有权
标题翻译：通过使用高温氧化物作为顶部氧化物和外围栅极氧化物的集成方法
公开(公告)号：US06117730A
公开(公告)日：2000-09-12
申请号：US427402
申请日：1999-10-25
申请人： Hideki Komori , Kenneth Au , Mark Ramsbey
发明人： Hideki Komori , Kenneth Au , Mark Ramsbey
IPC分类号： H01L21/8246 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/11526 , H01L27/11546 , Y10S438/954
摘要： A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.
摘要翻译：用于制造具有芯和外围的MONOS型闪存单元的ONO结构的工艺包括提供半导体衬底。生长在半导体衬底上的第一氧化硅层，并且沉积氮化硅层覆盖在氧化硅层上。在沉积ONO结构的第二氧化硅层之前，执行位线掩模以在芯处形成至少一个位线。此后，形成ONO掩模以在周边蚀刻期间保护ONO结构。在沉积和清洁用于位线形成和外围蚀刻的掩模之后，使用HTO沉积工艺沉积第二氧化硅层以覆盖氮化硅层。通过在形成ONO和位线掩模之后沉积第二氧化硅层，防止第二氧化硅层的劣化，并且顶部氧化硅层保持高质量。

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