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21. 发明申请

US20070007573A1 Controlled equivalent series resistance capacitor 有权
标题翻译：受控等效串联电阻电容
公开(公告)号：US20070007573A1
公开(公告)日：2007-01-11
申请号：US11177805
申请日：2005-07-08
申请人： Michael Hill , Kemal Aygun , Kimberly Eilert , Kaladhar Radhakrishnan
发明人： Michael Hill , Kemal Aygun , Kimberly Eilert , Kaladhar Radhakrishnan
IPC分类号： H01L29/94
CPC分类号： H01G4/232 , H01G4/30 , H01L28/60
摘要： Some embodiments of the present invention include capacitors with controlled equivalent series resistance.
摘要翻译：本发明的一些实施例包括具有受控等效串联电阻的电容器。

22. 发明申请

US20190229056A1 BRIDGE DIE DESIGN FOR HIGH BANDWIDTH MEMORY INTERFACE 审中-公开
公开(公告)号：US20190229056A1
公开(公告)日：2019-07-25
申请号：US16305758
申请日：2016-06-30
申请人： Zhiguo Qian , Kemal Aygun , Dae-Woo Kim , Jackie C. Preciado
发明人： Zhiguo Qian , Kemal Aygun , Dae-Woo Kim , Jackie C. Preciado
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00
摘要： A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

23. 发明申请

US20170287591A1 HELICALLY INSULATED TWINAX CABLE SYSTEMS AND METHODS 有权
公开(公告)号：US20170287591A1
公开(公告)日：2017-10-05
申请号：US15088924
申请日：2016-04-01
申请人： Zhichao Zhang , Gong Ouyang , Kai Xiao , Eric J. Li , Kemal Aygun
发明人： Zhichao Zhang , Gong Ouyang , Kai Xiao , Eric J. Li , Kemal Aygun
IPC分类号： H01B7/02 , H01B13/08 , H01B13/22 , H05K9/00
CPC分类号： H01B7/0241 , H01B11/1856 , H01B11/20 , H01B13/08 , H01B13/22 , H05K9/0098
摘要： A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.

24. 发明授权

US09240377B2 X-line routing for dense multi-chip-package interconnects 有权
公开(公告)号：US09240377B2
公开(公告)日：2016-01-19
申请号：US14579073
申请日：2014-12-22
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/532 , H01L23/538 , H01L23/528 , H01L25/10 , H01L23/498
CPC分类号： H01L23/53228 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

25. 发明申请

US20140071646A1 ROUTING DESIGN FOR HIGH SPEED INPUT/OUTPUT LINKS 有权
标题翻译：高速输入/输出链路的路由设计
公开(公告)号：US20140071646A1
公开(公告)日：2014-03-13
申请号：US13610663
申请日：2012-09-11
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H05K1/02 , H05K3/46
CPC分类号： H05K1/0228 , H05K1/0219 , H05K1/0243 , H05K1/113 , H05K3/4644 , H05K2201/09336 , H05K2201/09672 , H05K2201/09709 , H05K2201/09727 , Y10T29/49155
摘要： Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.
摘要翻译：某些实施例涉及路由结构及其形成。在一个实施例中，路由结构包括包括第一层的第一区域，第一层包括交替的信号迹线和由电介质隔开的接地迹线。第一区域还包括第二层，其包括由电介质隔开的交替信号迹线和接地迹线，其中位于第一层接地迹线上方的第二层信号，以及位于第一层信号迹线上的第二层接地迹线。第一区域还可以包括交替信号和接地迹线的附加层。第一区域也可以形成有具有大于信号迹线的宽度的接地迹线。路由结构还可以包括包括跟踪耦合到其上的焊盘的第二区域。描述和要求保护其他实施例。

26. 发明授权

US08188594B2 Input/output package architectures 有权
标题翻译：输入/输出包体系结构
公开(公告)号：US08188594B2
公开(公告)日：2012-05-29
申请号：US12587175
申请日：2009-10-01
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/34 , H01L23/10 , H01L23/28 , H01L23/495 , H01L23/48 , H01L23/52 , H01L23/04
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

27. 发明授权

US07705447B2 Input/output package architectures, and methods of using same 有权
公开(公告)号：US07705447B2
公开(公告)日：2010-04-27
申请号：US12286212
申请日：2008-09-29
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/34 , H01L23/495 , H01L23/10 , H01L23/28
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

28. 发明申请

US20090322350A1 PRINTED CIRCUIT ASSEMBLY AND METHOD FOR MEASURING CHARACTERISTIC IMPEDANCE 审中-公开
标题翻译：印刷电路组件和测量特性阻抗的方法
公开(公告)号：US20090322350A1
公开(公告)日：2009-12-31
申请号：US12165327
申请日：2008-06-30
申请人： Kemal Aygun , Jaemin Shin
发明人： Kemal Aygun , Jaemin Shin
IPC分类号： G01R27/04
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0237 , H05K1/0298 , H05K2203/162
摘要： A printed circuit assembly is provided. The printed circuit assembly includes a plurality of signal layers and a plurality of test structures disposed within the plurality of signal layers, wherein each of the plurality of test structures comprises one of a microstrip and a stripline and wherein each of the plurality of test structures is to measure a characteristic impedance of each of the plurality of signal layers.
摘要翻译：提供印刷电路组件。印刷电路组件包括多个信号层和设置在多个信号层内的多个测试结构，其中多个测试结构中的每一个包括微带线和带状线之一，并且其中多个测试结构中的每一个以测量所述多个信号层中的每一个的特征阻抗。

29. 发明申请

US20080238587A1 PACKAGE EMBEDDED EQUALIZER 有权
标题翻译：包装嵌入式平衡器
公开(公告)号：US20080238587A1
公开(公告)日：2008-10-02
申请号：US11694765
申请日：2007-03-30
申请人： Jaemin Shin , Pascal A. Meier , Telesphor Kamgaing , Kemal Aygun
发明人： Jaemin Shin , Pascal A. Meier , Telesphor Kamgaing , Kemal Aygun
IPC分类号： H04B3/14
CPC分类号： H04B3/14 , H01L23/66 , H01L25/16 , H01L2924/0002 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H01L2924/00
摘要： A passive equalizer circuit is embedded within a substrate of a package containing an integrated circuit. It is believed that substantial reduction in uneven frequency dependent loss may be achieved for interconnects interconnecting the integrated circuit with other integrated circuits on a printed circuit board. Other aspects are described and claimed.
摘要翻译：无源均衡器电路嵌入在包含集成电路的封装的衬底内。据信，将集成电路与印刷电路板上的其他集成电路互连的互连可以实现不均匀的频率相关损耗的显着减少。描述和要求保护其他方面。

30. 发明申请

US20070134925A1 Package using array capacitor core 有权
标题翻译：封装采用阵列电容核心
公开(公告)号：US20070134925A1
公开(公告)日：2007-06-14
申请号：US11301470
申请日：2005-12-12
申请人： Kimberly Eilert , Kaladhar Radhakrishnan , Kemal Aygun , Michael Hill
发明人： Kimberly Eilert , Kaladhar Radhakrishnan , Kemal Aygun , Michael Hill
IPC分类号： H01L21/311
CPC分类号： H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/50 , H01L23/66 , H01L24/81 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/142 , H05K1/162 , H05K3/007 , H05K3/4602 , H05K3/4614 , H05K2201/09309 , H05K2203/0156 , H05K2203/061 , H01L2924/00
摘要： An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro-via area and provide electrical connections between the top substrate layers. The array capacitor structure is placed in contact with the micro-via area. The array capacitor structure is electrically connected to the micro-vias. The bottom substrate layers are formed on the array capacitor structure.
摘要翻译：本发明的一个实施例是一种制造封装衬底的技术。封装衬底包括顶部衬底层，阵列电容器和底部衬底层。顶层衬底层嵌入微通孔。微通孔具有微通孔区域，并且在顶部基底层之间提供电连接。阵列电容器结构与微通孔区域接触。阵列电容器结构电连接到微通孔。底部衬底层形成在阵列电容器结构上。

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