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21. 发明授权

US07067420B2 Methods for forming a metal layer on a semiconductor 有权
标题翻译：在半导体上形成金属层的方法
公开(公告)号：US07067420B2
公开(公告)日：2006-06-27
申请号：US10404360
申请日：2003-04-01
申请人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
发明人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
IPC分类号： H10L21/4763 , H10L21/20 , H10L21/44
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/45542 , C23C16/45553 , H01L21/28562 , H01L21/32051 , H01L21/76877
摘要： A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
摘要翻译：金属层形成在集成电路器件上，包括在集成电路衬底上形成绝缘层。通过选择性地蚀刻绝缘层从而部分地暴露衬底而形成接触孔。包括氮化钽的金属层使用包括钽元素的钽前体和与钽元素化学键合的至少一个结合元件在包括接触孔的绝缘层上形成。至少一个键合元件的一部分包括与钽元素配位键合的至少一个配体结合元件。形成金属层可以包括用基本上不含氢自由基的去除气体去除至少一些配体键合元件。可以使用化学气相沉积（CVD）或原子层沉积（ALD）工艺来形成金属层。可以在包括氮化钽的金属层上沉积铜或其它金属层。

22. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

23. 发明授权

US07550353B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07550353B2
公开(公告)日：2009-06-23
申请号：US11685644
申请日：2007-03-13
申请人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
发明人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
IPC分类号： H01L21/8236
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.
摘要翻译：用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案，并且在包括氢，氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。当栅极图案包括隧道绝缘层，金属氮化物层和金属层时，选择性再氧化工艺会修复栅极图案的蚀刻损伤，同时防止金属氮化物层和钨电极的氧化。

24. 发明申请

US20080121983A1 Gate and method of forming the same, and memory device and method of manufacturing the same 审中-公开
标题翻译：门及其形成方法，以及存储器件及其制造方法
公开(公告)号：US20080121983A1
公开(公告)日：2008-05-29
申请号：US11606899
申请日：2006-12-01
申请人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
发明人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/40117 , H01L29/4234
摘要： A gate of a memory device may include a charge trapping structure having a tunnel oxide layer, a charge storing layer, and a blocking layer on a semiconductor substrate; a conductive pattern on the charge trapping structure, the conductive pattern including metal nitride; an ohmic film on the conductive pattern; and a gate electrode on the ohmic film.
摘要翻译：存储器件的栅极可以包括在半导体衬底上具有隧道氧化物层，电荷存储层和阻挡层的电荷俘获结构; 电荷捕获结构上的导电图案，导电图案包括金属氮化物; 导电图案上的欧姆膜; 和欧姆膜上的栅电极。

25. 发明授权

US07211769B2 Heating chamber and method of heating a wafer 有权
标题翻译：加热室和加热晶片的方法
公开(公告)号：US07211769B2
公开(公告)日：2007-05-01
申请号：US10115111
申请日：2002-04-01
申请人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Ju-Young Yun , Gil-Heyun Choi
发明人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Ju-Young Yun , Gil-Heyun Choi
IPC分类号： F27B5/14
CPC分类号： H01L21/67109 , C30B25/10 , C30B31/14
摘要： A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.
摘要翻译：提供了可以在回流工艺期间使用以形成具有多层书写结构的金属布线的加热室和使用其加热晶片的方法。加热室可以在上部处理位置和下部装载位置之间上下移动，并且包括具有用于支撑晶片的支撑表面的基座，安装在基座上方的盖子，当与该支撑表面一起形成处理区域时基座放置在其升高的处理位置和用于加热摇摆的加热单元。在加热晶片的方法中，在将晶片加载到支撑表面之前，处理区域中的温度保持适于加热晶片，晶片被加载到支撑表面上，并且加载的晶片在处理区域中被加热。

26. 发明授权

US07098131B2 Methods for forming atomic layers and thin films including tantalum nitride and devices including the same 失效
标题翻译：用于形成原子层的方法和包括氮化钽的薄膜以及包括其的装置
公开(公告)号：US07098131B2
公开(公告)日：2006-08-29
申请号：US10856627
申请日：2004-05-28
申请人： Sang-Bom Kang , Byung-Hee Kim , Kyung-In Choi , Gil-Heyun Choi , You-Kyoung Lee , Seong-Geon Park
发明人： Sang-Bom Kang , Byung-Hee Kim , Kyung-In Choi , Gil-Heyun Choi , You-Kyoung Lee , Seong-Geon Park
IPC分类号： H01L21/4763
CPC分类号： C23C16/45553 , C23C16/34 , H01L21/28556 , H01L21/28562 , H01L21/76843
摘要： Atomic layers can be formed by introducing a tantalum amine derivative reactant onto a substrate, wherein the tantalum amine derivative has a formula: Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1–C6 alkyl functional group, chemisorbing a portion of the reactant on the substrate, removing non-chemisorbed reactant from the substrate and introducing a reacting gas onto the substrate to form a solid material on the substrate. Thin films comprising tantalum nitride (TaN) are also provided.
摘要翻译：可以通过将钽胺衍生物反应物引入到基底上来形成原子层，其中该钽胺衍生物具有下式：Ta（NR 1 N 2）其中R 1，R 2和R 3各自独立地为H（R 3）3，其中R 1，R 2和R 3各自独立地为H 或C 1 -C 6烷基官能团，化学吸附基材上的一部分反应物，从底物除去非化学吸附的反应物并将反应气体引入到衬底以在衬底上形成固体材料。还提供了包括氮化钽（TaN）的薄膜。

27. 发明申请

US20050136652A1 Semiconductor interconnection structure with TaN and method of forming the same 审中-公开
标题翻译：具有TaN的半导体互连结构及其形成方法
公开(公告)号：US20050136652A1
公开(公告)日：2005-06-23
申请号：US11046624
申请日：2005-01-28
申请人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi
发明人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi
IPC分类号： H01L21/28 , H01L21/768 , H01L23/532 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/7685 , H01L21/76802 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.
摘要翻译：结构包括依次层叠在半导体衬底上的扩散阻挡层图案，导电层图案，粘合层图案和氮化钽层图案。根据形成结构的方法，通过使用PVD，CVD或ALD工艺形成氮化钽层并且被图案化以形成氮化钽层图案。结构和方法防止诸如环形缺陷的过程故障，简化相关工艺，并且当在结构中形成通孔时，仅允许抗折射层相对容易地曝光。

28. 发明申请

US20050082625A1 Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
标题翻译：形成包括高k电介质层和电极阻挡层的电子器件的方法
公开(公告)号：US20050082625A1
公开(公告)日：2005-04-21
申请号：US10969564
申请日：2004-10-20
申请人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
发明人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28088 , H01L21/28194 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.
摘要翻译：形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。栅电极阻挡层和栅电极金属层可以由不同的材料形成。此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

29. 发明授权

US06876078B2 Semiconductor interconnection structure with TaN and method of forming the same 有权
公开(公告)号：US06876078B2
公开(公告)日：2005-04-05
申请号：US10461613
申请日：2003-06-13
申请人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi
发明人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi
IPC分类号： H01L21/28 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/7685 , H01L21/76802 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.

30. 发明授权

US08501606B2 Methods of forming wiring structures 有权
标题翻译：形成布线结构的方法
公开(公告)号：US08501606B2
公开(公告)日：2013-08-06
申请号：US12836081
申请日：2010-07-14
申请人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
发明人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66621 , H01L21/76831 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/4236 , H01L29/665 , H01L29/78
摘要： A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
摘要翻译：一种半导体存储器布线方法，包括：接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞，所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线，所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞，第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线，所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。

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