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21. 发明授权

US4797583A Level converting circuit for converting voltage levels, including a current amplifying arrangement 失效
标题翻译：用于转换电压电平的电平转换电路，包括电流放大装置
公开(公告)号：US4797583A
公开(公告)日：1989-01-10
申请号：US683501
申请日：1984-12-19
申请人： Masahiro Ueno , Kozaburo Kurita , Ikuro Masuda , Nobuaki Miyakawa
发明人： Masahiro Ueno , Kozaburo Kurita , Ikuro Masuda , Nobuaki Miyakawa
IPC分类号： H03F3/45 , G11C11/409 , G11C11/416 , G11C11/419 , H03G11/00 , H03K19/0175 , H03K19/0185 , H03K19/0944 , H03K19/092 , H03K17/04 , H03K19/01 , H03K19/094
CPC分类号： H03K19/018514 , H03K19/09448
摘要： A level converter for transforming differential input voltages into an output voltage comprises a voltage-current conversion circuit for transforming the differential input voltages into differential currents, a current detection circuit for detecting the differential currents, a current amplifying circuit for amplifying the differential currents in response to the output of the current detection circuit, and a current-voltage conversion circuit for transforming the amplified differential currents into an output voltage, thereby allowing fast operation and drastic level conversion.
摘要翻译：用于将差分输入电压变换为输出电压的电平转换器包括用于将差分输入电压变换为差分电流的电压 - 电流转换电路，用于检测差分电流的电流检测电路，用于在响应中放大差分电流的电流放大电路到电流检测电路的输出，以及用于将放大的差分电流变换为输出电压的电流 - 电压转换电路，从而允许快速操作和剧烈的电平转换。

22. 发明授权

US07403365B2 Over-current detection circuit and method for power-supply device 失效
标题翻译：过电流检测电路及电源装置的方法
公开(公告)号：US07403365B2
公开(公告)日：2008-07-22
申请号：US11505821
申请日：2006-08-18
申请人： Takashi Sase , Akihiko Kanouda , Yosuke Kawakubo , Kozaburo Kurita
发明人： Takashi Sase , Akihiko Kanouda , Yosuke Kawakubo , Kozaburo Kurita
IPC分类号： H02H9/08
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0009
摘要： An over-current detection circuit using the ON-voltage of a main MOSFET is provided, which is resistant to process variations of a main MOSFET and is not easily influenced by switching noise. Separately from a main MOSFET (Q1), a sense MOSFET (Q3) whose size is 1/m of the main MOSFET is provided and it is caused to be normally on. A DC ON-voltage generated when a current that is 1/m of an over-current value is caused to flow through the sense MOSFET is obtained as a reference voltage for over-current setting. The ON-voltage when the main MOSFET is on is sampled and held, and it is obtained as a DC voltage. These DC voltages are compared in a comparator (COMP).
摘要翻译：提供了使用主MOSFET的导通电压的过电流检测电路，其抵抗主MOSFET的工艺变化，并且不容易受到开关噪声的影响。与主MOSFET（Q1）分开，提供尺寸为主MOSFET的1 / m的感测MOSFET（Q 3），并使其正常导通。获得当使过电流值为1 / m的电流通过感测MOSFET流过时产生的直流导通电压作为过电流设定的基准电压。主MOSFET导通时的导通电压进行采样保持，作为直流电压获得。在比较器（COMP）中比较这些直流电压。

23. 发明申请

US20070188958A1 Over-current detection circuit and method for power-supply device 失效
标题翻译：过电流检测电路及电源装置的方法
公开(公告)号：US20070188958A1
公开(公告)日：2007-08-16
申请号：US11505821
申请日：2006-08-18
申请人： Takashi Sase , Akihiko Kanouda , Yosuke Kawakubo , Kozaburo Kurita
发明人： Takashi Sase , Akihiko Kanouda , Yosuke Kawakubo , Kozaburo Kurita
IPC分类号： H02H3/08 , H02H9/02
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0009
摘要： An over-current detection circuit using the ON-voltage of a main MOSFET is provided, which is resistant to process variations of a main MOSFET and is not easily influenced by switching noise. Separately from a main MOSFET (Q1), a sense MOSFET (Q3) whose size is 1/m of the main MOSFET is provided and it is caused to be normally on. A DC ON-voltage generated when a current that is 1/m of an over-current value is caused to flow through the sense MOSFET is obtained as a reference voltage for over-current setting. The ON-voltage when the main MOSFET is on is sampled and held, and it is obtained as a DC voltage. These DC voltages are compared in a comparator (COMP).
摘要翻译：提供了使用主MOSFET的导通电压的过电流检测电路，其抵抗主MOSFET的工艺变化，并且不容易受到开关噪声的影响。与主MOSFET（Q1）分开，提供尺寸为主MOSFET的1 / m的感测MOSFET（Q 3），并使其正常导通。获得当使过电流值为1 / m的电流通过感测MOSFET流过时产生的直流导通电压作为过电流设定的基准电压。主MOSFET导通时的导通电压进行采样保持，作为直流电压获得。在比较器（COMP）中比较这些直流电压。

24. 发明授权

US07113434B2 Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle 失效
标题翻译：具有用于产生具有时差的定时信号的可编程延迟的半导体集成电路是时钟周期的非整数倍
公开(公告)号：US07113434B2
公开(公告)日：2006-09-26
申请号：US10823664
申请日：2004-04-14
申请人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
发明人： Hiroshi Akasaki , Shuichi Miyaoka , Yuji Yokoyama , Masatoshi Hasegawa , Kozaburo Kurita
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C2207/104
摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
摘要翻译：在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍的时钟信号。

25. 发明授权

US06947514B1 Phase-locked loop circuit, information processing apparatus, and information processing system 失效
标题翻译：锁相环电路，信息处理装置和信息处理系统
公开(公告)号：US06947514B1
公开(公告)日：2005-09-20
申请号：US09446507
申请日：1998-06-26
申请人： Kazuo Kato , Takashi Sase , Takashi Hotta , Hirokazu Aoki , Kozaburo Kurita
发明人： Kazuo Kato , Takashi Sase , Takashi Hotta , Hirokazu Aoki , Kozaburo Kurita
IPC分类号： H03L7/113 , H03D3/24 , H03L7/06
CPC分类号： H03L7/113
摘要： A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.
摘要翻译：提供锁相环（PLL）电路以在宽带中操作，包括两个单独的环路，其中一个用于通过其关联比例控制单元将振荡器的输出反馈到同一个振荡器，而另一个用于通过集成控制单元将振荡器的输出反馈到同一个振荡器。比例控制单元被布置成控制振荡器的输出频率，并且可操作以基于输入和输出信号之间的差产生控制信号。积分控制单元被布置成控制振荡器的输出信号的相位，从而基于输入和输出信号之间的相位差产生控制信号。

26. 发明授权

US5974560A Information processor and information processing system utilizing clock signal 失效
标题翻译：信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5974560A
公开(公告)日：1999-10-26
申请号：US788831
申请日：1997-01-27
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

27. 发明授权

US5936441A Clock pulse generator 失效
标题翻译：时钟脉冲发生器
公开(公告)号：US5936441A
公开(公告)日：1999-08-10
申请号：US857202
申请日：1997-05-15
申请人： Kozaburo Kurita
发明人： Kozaburo Kurita
IPC分类号： H03K3/0231 , H03K3/03 , H03K3/354 , H03K5/13 , H03L7/07 , H03L7/081 , H03L7/099 , H03L7/10 , H03L7/00
CPC分类号： H03L7/0805 , H03K3/0231 , H03K3/03 , H03K3/0322 , H03K5/133 , H03L7/07 , H03L7/0812 , H03L7/0995
摘要： A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal. This current signal is combined with the current signal from the compensation circuit to control the oscillation frequency of a ring oscillator comprising a current-controlled delay circuit the same in structure as the above current-controlled delay circuit. On the basis of the oscillation signal from the ring oscillator, the second frequency signal and clock signals needed in the semiconductor integrated circuit are generated.
摘要翻译：响应于从半导体集成电路外部馈送的定时信号，在宽频率范围内稳定地运行的简单结构的时钟脉冲发生器。从半导体集成电路的外部端子馈送的第一频率信号和在半导体集成电路内产生的第二频率信号被输入到相位比较器。相位比较器的输出信号由低通滤波器平滑，用于转换为电压信号。补偿电路使用来自接收第一频率信号的电流控制延迟电路的延迟信号和第一频率信号来产生对应于后一信号的频率的电流信号。由低通滤波器产生的电压信号被转换为电流信号。该电流信号与来自补偿电路的电流信号组合，以控制包括与上述电流控制延迟电路相同结构的电流控制延迟电路的环形振荡器的振荡频率。基于来自环形振荡器的振荡信号，生成半导体集成电路中所需的第二频率信号和时钟信号。

28. 发明授权

US5412262A Semiconductor integrated circuit device having plurality of supply potential lines connected thereto, and system employing the same 失效
标题翻译：具有与其连接的多个电源电位线的半导体集成电路器件及其系统
公开(公告)号：US5412262A
公开(公告)日：1995-05-02
申请号：US279626
申请日：1994-07-25
申请人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
发明人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
IPC分类号： H03K19/00 , H01L27/02 , H03K19/0175 , H03K19/0185 , H03K19/02
CPC分类号： H03K19/017527 , H03K19/018521 , H01L27/0214
摘要： In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.
摘要翻译：在其中多个半导体集成电路器件共存并且其中布置多条电源线的系统中，TTL接口LSI和ECL接口LSI的主电源被共享，以便减少电源电位线的数量。此外，在与例如TTL和ECL接口LSI接口的BiCMOS LSI的LSI具有约3V的器件耐受电压的情况下，允许与两者的两端的电源电压| 5V | 的TTL接口LSI的主电源和电源电压| 2 V | 由于电源电压具有3V的差异，所以ECL接口LSI的射极跟随器部分的电源。

29. 发明授权

US5133064A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US5133064A
公开(公告)日：1992-07-21
申请号：US184782
申请日：1988-04-22
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

30. 发明授权

US5047669A Tristate circuit using bipolar transistor and CMOS transistor 失效
标题翻译：三态电路采用双极晶体管和CMOS晶体管
公开(公告)号：US5047669A
公开(公告)日：1991-09-10
申请号：US318689
申请日：1989-03-03
申请人： Masahiro Iwamura , Kozaburo Kurita , Hideo Maejima , Tetsuo Nakano , Atsuo Hotta
发明人： Masahiro Iwamura , Kozaburo Kurita , Hideo Maejima , Tetsuo Nakano , Atsuo Hotta
IPC分类号： H03K17/567 , H03K19/003 , H03K19/0175 , H03K19/08 , H03K19/094 , H03K19/0944
CPC分类号： H03K17/567 , H03K19/00307 , H03K19/09429 , H03K19/09448
摘要： In a semiconductor integrated circuit, drain-source paths of an NMOS transistor and a PMOS transistor are connected between the base and emitter of a bipolar transistor, and control signals are applied to gates of the NMOS transistor and the PMOS transistor so as to keep the NMOS transistor and the PMOS transistor at OFF condition when the bipolar transistor is operating and so as to keep the NMOS transistor and the PMOS transistor at ON condition when the bipolar transistor is in the quiescent state.

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