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21. 发明授权

US06727544B2 Semiconductor memory including cell(s) with both charge storage layer(s) and control gate laterally surrounding island-like semiconductor layer 有权
标题翻译：半导体存储器包括具有两个电荷存储层的电池和控制栅极横向周围的岛状半导体层
公开(公告)号：US06727544B2
公开(公告)日：2004-04-27
申请号：US10107380
申请日：2002-03-28
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.
摘要翻译：半导体存储器包括：衬底; 以及由至少一个岛状半导体层，电荷存储层和控制栅极构成的一个或多个存储单元，电荷存储层和控制栅极被形成为完全或部分地环绕岛状半导体层的侧壁，其中所述一个或多个存储单元中的至少一个与所述半导体衬底电绝缘，并且具有允许电荷至少在所述电荷存储层和岛状半导体层之间的区域的一部分通过的绝缘膜。

22. 发明授权

US07141506B2 Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same 有权
标题翻译：用于评估半导体衬底的性能对平面取向的依赖性的方法和使用其的半导体器件
公开(公告)号：US07141506B2
公开(公告)日：2006-11-28
申请号：US10175076
申请日：2002-06-20
申请人： Tetsuo Endoh , Fujio Masuoka , Noboru Takeuchi , Takuji Tanigami , Takashi Yokoyama
发明人： Tetsuo Endoh , Fujio Masuoka , Noboru Takeuchi , Takuji Tanigami , Takashi Yokoyama
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.
摘要翻译：用于评估半导体衬底的平面取向依赖性的方法包括：在具有平面取向的半导体衬底上形成硬掩模（100）; 使用硬掩模作为掩模对半导体衬底进行各向异性蚀刻，以获得以特定晶体取向的表面; 以及通过使用以特定晶体取向取向的至少一部分表面来评估半导体衬底的平面取向依赖性。

23. 发明授权

US07135726B2 Semiconductor memory and its production process 有权
公开(公告)号：US07135726B2
公开(公告)日：2006-11-14
申请号：US09925952
申请日：2001-08-10
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10864 , H01L27/11 , H01L27/1104 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

24. 发明授权

US07061038B2 Semiconductor memory device and its production process 有权
标题翻译：半导体存储器件及其生产工艺
公开(公告)号：US07061038B2
公开(公告)日：2006-06-13
申请号：US10727266
申请日：2003-12-04
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11519 , H01L27/11553 , H01L27/11556 , H01L27/11568 , H01L27/1203 , H01L29/0692 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电型半导体衬底; 以及由在半导体衬底上形成的岛状半导体层和电荷存储层和控制栅极构成的多个存储单元，其形成在岛状半导体层的侧壁的整个或部分周围，其中，多个存储单元被串联设置，构成存储单元的岛状半导体层具有在半导体衬底的水平方向上分级变化的横截面区域，并且能够至少在岛状半导体层的与半导体衬底水平的平面的一部分。

25. 发明申请

US20050101087A1 Semiconductor memory device and its production process 有权
标题翻译：半导体存储器件及其生产工艺
公开(公告)号：US20050101087A1
公开(公告)日：2005-05-12
申请号：US10727266
申请日：2003-12-04
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/84 , H01L27/02 , H01L27/115 , H01L27/12 , H01L29/06 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0207 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11519 , H01L27/11553 , H01L27/11556 , H01L27/11568 , H01L27/1203 , H01L29/0692 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电型半导体衬底; 以及由在半导体衬底上形成的岛状半导体层和电荷存储层和控制栅极构成的多个存储单元，其形成在岛状半导体层的侧壁的整个或部分周围，其中，多个存储单元被串联设置，构成存储单元的岛状半导体层具有在半导体衬底的水平方向上分级变化的横截面区域，并且能够至少在岛状半导体层的与半导体衬底水平的平面的一部分。

26. 发明授权

US06593231B2 Process of manufacturing electron microscopic sample and process of analyzing semiconductor device 有权
公开(公告)号：US06593231B2
公开(公告)日：2003-07-15
申请号：US10093712
申请日：2002-03-11
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L214763
CPC分类号： G01N23/04
摘要： A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

27. 发明授权

US06933556B2 Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer 有权
标题翻译：栅极的半导体存储器至少部分地位于垂直取向的半导体层中限定的凹部中
公开(公告)号：US06933556B2
公开(公告)日：2005-08-23
申请号：US10174903
申请日：2002-06-20
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.
摘要翻译：半导体存储器包括：第一导电型半导体衬底和一个或多个存储单元，每个存储单元由在其侧壁上具有凹部的岛状半导体层构成，电荷存储层，形成为完全或部分地环绕岛状半导体层的侧壁，形成在电荷存储层上的控制栅极，其中所述一个或多个存储单元的至少一个电荷存储层部分位于形成在岛状半导体层的侧壁上的凹槽内。

28. 发明授权

US07315059B2 Semiconductor memory device and manufacturing method for the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07315059B2
公开(公告)日：2008-01-01
申请号：US10854555
申请日：2004-05-25
申请人： Tetsuo Endoh , Fujio Masuoka , Shinji Horii , Takuji Tanigami , Yoshihisa Wada , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Shinji Horii , Takuji Tanigami , Yoshihisa Wada , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L29/792
CPC分类号： H01L27/11556 , H01L27/115
摘要： The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.
摘要翻译：本发明提供了一种半导体存储器件，其具有在突出的半导体层的表面上形成在第一导电类型的半导体衬底上的多个突出半导体层和多个存储单元，其中每个存储单元由电荷形成存储层，控制栅极和第二导电类型的杂质扩散层形成在突出半导体层和多个存储单元的一部分中，至少沿预定方向排列，并且多个栅极的控制栅极将存储单元与预定方向对准地被放置成彼此分离。

29. 发明申请

US20100283097A1 MOS SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： MOS半导体存储器件
公开(公告)号：US20100283097A1
公开(公告)日：2010-11-11
申请号：US12665534
申请日：2008-06-20
申请人： Tetsuo Endoh , Masayuki Kohno , Tatsuo Nishita , Minoru Honda , Toshio Nakanishi , Yoshihiro Hirota
发明人： Tetsuo Endoh , Masayuki Kohno , Tatsuo Nishita , Minoru Honda , Toshio Nakanishi , Yoshihiro Hirota
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , C23C16/308 , C23C16/345 , G11C11/5628 , G11C16/0466 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/7926
摘要： The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.
摘要翻译：本发明提供一种实现优异的数据保持特性的MOS半导体存储器件，同时还实现了高速数据写入性能，低功率操作性能和高可靠性。 MOS半导体存储器件601包括具有较大带隙111a和115a的第一绝缘膜111和第五绝缘膜115，具有最小带隙113a的第三绝缘膜113和介于第三绝缘膜113之间的第二绝缘膜112和第四绝缘膜114。绝缘膜113和第一和第五绝缘膜111和115，并具有中间带隙112a和114a。

30. 发明授权

US08969944B2 Semiconductor integrated circuit and method of producing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US08969944B2
公开(公告)日：2015-03-03
申请号：US13697905
申请日：2011-05-13
申请人： Tetsuo Endoh , Seo Moon-Sik
发明人： Tetsuo Endoh , Seo Moon-Sik
IPC分类号： H01L29/792
CPC分类号： H01L27/11556 , G11C16/0425 , G11C16/0433 , G11C16/0483 , H01L27/088 , H01L27/11524 , H01L27/11551 , H01L29/42328 , H01L29/66477 , H01L29/66825 , H01L29/7883 , H01L29/7889
摘要： Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.
摘要翻译：提供了一种半导体集成电路，其使用在电池之间没有干扰的新颖的垂直MOS晶体管，其能够使短沟道效应最小化，不具有热电子注入，并且不需要形成浅结。还提供了一种制造半导体集成电路的方法。半导体集成电路中的存储单元1设置有：作为通道的半导体柱2; 通过半导体柱2的外周上的隧道绝缘层6周向地覆盖半导体柱2的浮动栅极5; 以及通过半导体柱2的外周上的绝缘层8周向地覆盖半导体柱的控制栅极4，并且经由浮动栅极的外周上的绝缘层7周向地覆盖浮置栅极5。

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