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21. 发明授权

US09087581B2 Cross point variable resistance nonvolatile memory device and method of writing thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US09087581B2
公开(公告)日：2015-07-21
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

22. 发明授权

US08665633B2 Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device 有权
标题翻译：非易失性可变电阻存储元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US08665633B2
公开(公告)日：2014-03-04
申请号：US13599406
申请日：2012-08-30
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.
摘要翻译：根据施加电压的极性将数据写入可变电阻元件（10a）的方法，该可变电阻元件（10a）根据施加的电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为对上电极（11）相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件设置为低电阻状态（403,402）; 并且在低电阻写入步骤中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件通过低电阻状态设置为高电阻状态。

23. 发明申请

US20130114327A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20130114327A1
公开(公告)日：2013-05-09
申请号：US13639120
申请日：2012-05-30
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/72
摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.
摘要翻译：一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且用最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

24. 发明申请

US20130003439A1 NONVOLATILE VARIABLE RESISTANCE MEMORY ELEMENT WRITING METHOD, AND NONVOLATILE VARIABLE RESISTANCE MEMORY DEVICE 有权
标题翻译：非易失性可变电阻记忆元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US20130003439A1
公开(公告)日：2013-01-03
申请号：US13599406
申请日：2012-08-30
申请人： Ryotaro AZUMA , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro AZUMA , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.
摘要翻译：根据施加电压的极性将数据写入可变电阻元件（10a）的方法，该可变电阻元件（10a）根据施加的电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为对上电极（11）相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件设置为低电阻状态（403,402）; 并且在低电阻写入步骤中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件通过低电阻状态设置为高电阻状态。

25. 发明授权

US08198618B2 Nonvolatile memory device and manufacturing method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08198618B2
公开(公告)日：2012-06-12
申请号：US12747060
申请日：2008-12-02
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).
摘要翻译：本发明的非易失性存储装置包括基板（1），第一布线（3），分别填充到第一通孔（4）中的第一填充构件（5），分别穿过第一布线 3）分别垂直于第一导线（3），每个第二导线（11）包括多个层，包括第一电阻可变元件中的每一个的电阻变化层（6），导电层（7）和按顺序堆叠在一起的第二电阻可变元件的电阻变化层（8），分别填充到第二通孔（13）中的第二填充组分（14）和第三导线（15），以及导电层第二电线（11）的电极（7）用作第一电阻可变元件（9）的电极和第二电阻可变元件（10）的电极。

26. 发明申请

US20110128773A1 NONVOLATILE VARIABLE RESISTANCE MEMORY ELEMENT WRITING METHOD, AND NONVOLATILE VARIABLE RESISTANCE MEMORY DEVICE 有权
标题翻译：非易失性可变电阻记忆元件写入方法和非易失性可变电阻存储器件
公开(公告)号：US20110128773A1
公开(公告)日：2011-06-02
申请号：US12999019
申请日：2010-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Shunsaku Muraoka , Ken Kawai
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).
摘要翻译：为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻州（401）。

27. 发明申请

US20100258779A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING MEHTOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100258779A1
公开(公告)日：2010-10-14
申请号：US12745190
申请日：2008-11-06
申请人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Takumi Mikawa , Kenji Tominaga , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).
摘要翻译：本发明的非易失性存储器件包括填充在第一通孔（4）中的基片（1），第一布线（3），第一电阻可变元件（5）和第一二极管元件的下电极（6）分别与第一布线3分别垂直于第一布线3交叉的第二布线（11），每条布线包括第一二极管元件的半导体层（7），导电层（8）和半导体层（ 10）分别被填充到第二通孔（13）中的第二电阻可变元件（16）和第二二极管元件的上电极（14）以及第三电线（17）），并且每个第二布线（11）的导电层（8）也用作第一二极管元件（9）的上电极和第二二极管元件（15）的下电极。

28. 发明授权

US08953363B2 Nonvolatile semiconductor memory device and read method for the same 有权
标题翻译：非易失性半导体存储器件及其读取方法相同
公开(公告)号：US08953363B2
公开(公告)日：2015-02-10
申请号：US13700329
申请日：2012-07-11
申请人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
发明人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C7/14
CPC分类号： G11C13/004 , G11C7/14 , G11C11/1673 , G11C13/0004 , G11C2013/0054 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/77
摘要： A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
摘要翻译：提供一种能够抑制潜流引起的对存储元件的电阻值的检测灵敏度的降低的交叉点非易失性存储装置。该设备包括垂直位和字线; 交叉点单元阵列，其包括存储单元，每个存储单元具有电阻值，该电阻值根据电信号在至少两个电阻状态之间可逆地改变;布置在字和位线的交叉点上; 偏移检测单元阵列，包括在高电阻状态下具有高于存储单元的电阻的偏移检测单元，所述字线由偏移检测单元阵列共享; 读取电路（读出放大器），其基于通过所选位线的电流确定所选存储单元的电阻状态; 以及在读取操作时段中向偏移检测单元阵列提供电流的电流源。

29. 发明申请

US20140112054A1 CROSSPOINT NONVOLATILE MEMORY DEVICE AND FORMING METHOD THEREOF 有权
标题翻译： CROSSPOINT非易失性存储器件及其形成方法
公开(公告)号：US20140112054A1
公开(公告)日：2014-04-24
申请号：US13983314
申请日：2012-11-13
申请人： Kazuhiko Shimakawa , Akifumi Kawahara , Ryotaro Azuma , Ken Kawai
发明人： Kazuhiko Shimakawa , Akifumi Kawahara , Ryotaro Azuma , Ken Kawai
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0002 , G11C13/0007 , G11C13/0038
摘要： A sense amplification circuit includes a sneak current compensating load current supply unit that selectively switches a load current among load currents having different current amounts and supplies the load current to a bit line selected by a column selection circuit. The sense amplification circuit outputs ‘L’ level when a current amount of the load current is more than a reference current amount, and outputs ‘H’ level when the current amount is less than the reference current amount. A control circuit adjusts the current amount to a predetermined current amount that causes the sense amplification circuit to output ‘H’ level. After the adjustment, the control circuit performs control to supply the load current having the predetermined current amount and controls the writing unit to keep the application until the sense amplification circuit outputs ‘L’ level.
摘要翻译：感测放大电路包括潜流补偿负载电流供应单元，其选择性地切换具有不同电流量的负载电流之间的负载电流，并将负载电流提供给由列选择电路选择的位线。当负载电流的当前量大于参考电流量时，感测放大电路输出“L”电平，当电流量小于基准电流量时，输出“H”电平。控制电路将电流量调整到使得感测放大电路输出“H”电平的预定电流量。在调整之后，控制电路进行控制以提供具有预定电流量的负载电流，并且控制写入单元以保持应用直到读出放大电路输出“L”电平。

30. 发明授权

US08467229B2 Variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US08467229B2
公开(公告)日：2013-06-18
申请号：US13511787
申请日：2011-11-24
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
摘要翻译：在非易失性存储器件中，基本阵列平面（0至3）具有各自的第一通孔组（121至124），其仅互连基本阵列平面中的偶数位线，以及相互连接的相应的第二通孔组（131至134）在基本阵列平面中只有奇数位线，在第一基本阵列平面中的第一通孔组和与Y方向上与第一基本阵列平面相邻的第二基本阵列平面中的第二通孔组彼此相邻， Y方向和第二基本阵列平面中的第一通孔组连接到具有固定电位的未选择位线专用全局位线（GBL_NS），当第一基本阵列平面中的第一通孔组连接到与第一个基本阵列平面相关的第一个全局位线。

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