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21. 发明申请

US20100097092A1 CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS 有权
标题翻译：集成电路闭环反馈控制
公开(公告)号：US20100097092A1
公开(公告)日：2010-04-22
申请号：US12651244
申请日：2009-12-31
申请人： Kleanthes G. Koniaris , James B. Burr
发明人： Kleanthes G. Koniaris , James B. Burr
IPC分类号： G01R31/28
CPC分类号： H03K3/012 , G01R31/2621 , G05B13/021 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03K3/0315 , Y02D10/126 , Y02D10/172
摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
摘要翻译：集成电路闭环反馈控制系统与方法。在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。

22. 发明申请

US20100072575A1 LAYOUT PATTERNS FOR DEEP WELL REGION TO FACILITATE ROUTING BODY-BIAS VOLTAGE 失效
标题翻译：深层布局布局模式，以便更轻松地布线身体偏心电压
公开(公告)号：US20100072575A1
公开(公告)日：2010-03-25
申请号：US12628011
申请日：2009-11-30
申请人： Mike Pelham , James B. Burr
发明人： Mike Pelham , James B. Burr
IPC分类号： H01L29/06
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
摘要翻译：提供并描述了深阱区域的布局图案，以便于在半导体器件中布置体偏置电压。布局图案包括对角子表面网格结构，轴向子表面网格结构，对角子表面条带结构和轴向子表面条带结构。根据几个因素，为半导体器件的区域选择特定的布局图案。

23. 发明授权

US07683442B1 Raised source/drain with super steep retrograde channel 有权
标题翻译：用超级陡峭的逆行通道引起源/漏
公开(公告)号：US07683442B1
公开(公告)日：2010-03-23
申请号：US11529972
申请日：2006-09-29
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with the present invention may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译：具有超陡逆行通道的升高源/漏源的系统和方法。根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。半导体器件还包括形成在表面下方深度的超陡逆行通道区域。深度约为栅极氧化物厚度的十至三十倍。根据本发明的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

24. 发明申请

US20080135905A1 SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：用于集成电路设备中的身体偏置电压的电压馈电的选择性耦合
公开(公告)号：US20080135905A1
公开(公告)日：2008-06-12
申请号：US12033840
申请日：2008-02-19
申请人： James B. Burr , Robert Fu
发明人： James B. Burr , Robert Fu
IPC分类号： H01L23/50 , G11C5/14
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.
摘要翻译：一种具有体偏置电压机构的集成电路器件。集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。可以可选地提供用于与第一外部设置的销连接的第一垫。第一个焊盘用于接收外部施加的主体偏置电压。用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。电源电压可以在集成电路内部获得。

25. 发明授权

US06838328B1 Back-biased MOS device fabrication method 有权
标题翻译：背偏MOS器件制造方法
公开(公告)号：US06838328B1
公开(公告)日：2005-01-04
申请号：US10683957
申请日：2003-10-10
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L21/425
CPC分类号： H01L21/823892 , H01L21/761 , H01L21/823878 , H01L27/092
摘要： A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

26. 发明授权

US06831494B1 Voltage compensated integrated circuits 有权
标题翻译：电压补偿集成电路
公开(公告)号：US06831494B1
公开(公告)日：2004-12-14
申请号：US10439665
申请日：2003-05-16
申请人： Robert Fu , Neal A. Osborn , James B. Burr
发明人： Robert Fu , Neal A. Osborn , James B. Burr
IPC分类号： H03K3037
CPC分类号： H03K3/011 , H03K3/0315
摘要： A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.
摘要翻译：一种电压补偿集成电路的方法和系统。通过施加电压补偿来增强集成电路的工作特性。

27. 发明授权

US06781213B2 Device including a resistive path to introduce an equivalent RC circuit 有权
公开(公告)号：US06781213B2
公开(公告)日：2004-08-24
申请号：US10393534
申请日：2003-03-20
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： H01L2900
CPC分类号： H01L27/092 , H01L27/0727 , H01L29/1087 , H01L29/8605
摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

28. 发明授权

US6048746A Method for making die-compensated threshold tuning circuit 失效
标题翻译：制造芯片补偿阈值调谐电路的方法
公开(公告)号：US6048746A
公开(公告)日：2000-04-11
申请号：US92906
申请日：1998-06-08
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： G01R31/26 , G01R31/27 , H01L21/66
CPC分类号： G01R31/275 , G01R31/2621
摘要： To compensate for process, activity and environmental variations in a semiconductor device, a back-bias potential tuning circuit is formed on a semiconductor die. The tuning circuit tunes a bias potential applied to the semiconductor die to maintain a predetermined ratio between a transistor on-current and a transistor off-current through at least one channel region. Then, a leakage current is measured for multiple transistors formed in the semiconductor die to determine a representative leakage of the semiconductor die. Tuning characteristics of the back-bias potential tuning circuit are then set to match the representative leakage of the semiconductor die.
摘要翻译：为了补偿半导体器件中的工艺，活性和环境变化，在半导体管芯上形成背偏电位调谐电路。调谐电路调节施加到半导体管芯的偏置电位，以保持晶体管导通电流和通过至少一个沟道区域的晶体管截止电流之间的预定比率。然后，对形成在半导体管芯中的多个晶体管测量泄漏电流，以确定半导体管芯的代表性泄漏。然后设置背偏电位调谐电路的调谐特性以匹配半导体管芯的代表性泄漏。

29. 发明授权

US5998850A Tunable field plate 失效
标题翻译：可调场地板
公开(公告)号：US5998850A
公开(公告)日：1999-12-07
申请号：US28457
申请日：1998-02-24
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： H01L21/762 , H01L21/765 , H01L27/14
CPC分类号： H01L21/76202 , H01L21/765 , Y10S257/921
摘要： First and second semiconductor devices are separated by a field oxide on a semiconductor substrate, and a field plate is positioned over the field oxide. A leakage detector detects a field leakage current between the first and second semiconductor devices. A field plate generator tunes a potential of said field plate according to a magnitude of the field current detected by the leakage current detector. In this manner, field leakage is optimized, and total dose effects may be monitored for signs of device failure.
摘要翻译：第一和第二半导体器件由半导体衬底上的场氧化物分隔开，并且场板位于场氧化物上方。泄漏检测器检测第一和第二半导体器件之间的场漏电流。场板发生器根据由漏电流检测器检测的励磁电流的大小调谐所述场板的电位。以这种方式，对场泄漏进行了优化，并且可以监测总体剂量效应以用于设备故障的迹象。

30. 发明授权

US5985727A Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface 失效
标题翻译：用于形成埋置在衬底表面中的逆行袋区和反掺杂区的MOS器件的方法
公开(公告)号：US5985727A
公开(公告)日：1999-11-16
申请号：US885071
申请日：1997-06-30
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7835
摘要： Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.
摘要翻译：公开了具有分级浓度分布的口袋区域的低阈值非对称MOS器件。袋区域包括与器件的沟道区域相对的源或漏侧的器件的源极或漏极的相对高的掺杂剂原子浓度（与体区相同的导电类型）。口袋区域的渐变浓度分布在基底表面附近提供较低的掺杂剂浓度，并且在该表面下方增加的掺杂剂浓度。这提供了通过袋区域的相对较低的电阻传导路径，同时允许器件的阈值电压在口袋区域稍高一些。不对称装置还可以包括位于其衬底表面下方的反掺杂剂区域。这迫使电流在衬底中流动，但刚好高于高对位掺杂剂浓度的区域，其中电阻相对较低。

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