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21. 发明授权

US07900071B2 Apparatus and method to manage power in a computing device 失效
标题翻译：在计算设备中管理功率的装置和方法
公开(公告)号：US07900071B2
公开(公告)日：2011-03-01
申请号：US12031543
申请日：2008-02-14
申请人： Robert H. Bell, Jr. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Michael Declan Roll
发明人： Robert H. Bell, Jr. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Michael Declan Roll
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , Y02D10/16
摘要： A method to manage power in a computing device comprising a controller assembly and a storage assembly comprising a plurality of data storage devices, by selecting a processor parameter, establishing a threshold processor parameter value, establishing a threshold over-parameter time interval, selecting a data storage device parameter, and establishing a nominal data storage device parameter value. The method determines an actual processor parameter value. If the actual processor parameter value is less than or equal to the threshold processor parameter value, the method operates each of the plurality of data storage devices using the nominal data storage device parameter value. If the actual processor parameter value is greater than the threshold processor parameter value, then the method determines an actual over-parameter time interval. If the actual processor parameter value is greater than the threshold processor parameter value, and if the actual over-parameter time interval is greater than the threshold over-parameter time interval, then the method operates each of the plurality of data storage devices using a data storage device parameter value less than the nominal data storage device parameter value.
摘要翻译：一种通过选择处理器参数，建立阈值处理器参数值，建立阈值超参数时间间隔，选择数据的方法来管理计算设备中的功率的方法，包括控制器组件和包括多个数据存储设备的存储组件存储设备参数，并建立标称数据存储设备参数值。该方法确定实际的处理器参数值。如果实际处理器参数值小于或等于阈值处理器参数值，则该方法使用标称数据存储设备参数值来操作多个数据存储设备中的每一个。如果实际处理器参数值大于阈值处理器参数值，则该方法确定实际的超参数时间间隔。如果实际处理器参数值大于阈值处理器参数值，并且如果实际超参数时间间隔大于阈值过参数时间间隔，则该方法使用数据来操作多个数据存储设备中的每一个存储设备参数值小于额定数据存储设备参数值。

22. 发明授权

US07840758B2 Variable store gather window 有权
标题翻译：变量存储收集窗口
公开(公告)号：US07840758B2
公开(公告)日：2010-11-23
申请号：US11689990
申请日：2007-03-22
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

23. 发明授权

US07543109B1 System and method for caching data in a blade server complex 失效
标题翻译：用于在刀片服务器组合中缓存数据的系统和方法
公开(公告)号：US07543109B1
公开(公告)日：2009-06-02
申请号：US12122448
申请日：2008-05-16
申请人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, Jr. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/0888
摘要： A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of the pages. A processor blade is provided that includes a first memory area to store at least one of the pages and a second memory area configured to store an address of each of the pages and a hint value that is assigned to each of the pages. An address of each of the pages is stored in the second memory area, and a hint is assigned to each of the pages, where the hint is one of: likely to be accessed, may be accessed, and unlikely to be accessed. The page is then stored in storage blade cache memory based on the hint.
摘要翻译：一种用于在刀片计算复合体中缓存数据的方法包括提供包括可操作以存储数据页的盘的存储刀片和可存储至少一个页的高速缓冲存储器。提供了一种处理器刀片，其包括用于存储所述页面中的至少一个的第一存储器区域和被配置为存储每个页面的地址的第二存储器区域以及分配给每个页面的提示值。每个页面的地址被存储在第二存储器区域中，并且提示被分配给每个页面，其中提示是可能被访问的，可能被访问并且不可能被访问。然后基于提示将该页面存储在存储刀片缓存中。

24. 发明授权

US07363433B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07363433B2
公开(公告)日：2008-04-22
申请号：US11054390
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

25. 发明授权

US06950892B2 Method and system for managing distributed arbitration for multicycle data transfer requests 失效
标题翻译：用于管理多周期数据传输请求的分布式仲裁的方法和系统
公开(公告)号：US06950892B2
公开(公告)日：2005-09-27
申请号：US10411463
申请日：2003-04-10
申请人： Robert H. Bell, Jr. , Robert Alan Cargnoni
发明人： Robert H. Bell, Jr. , Robert Alan Cargnoni
IPC分类号： G06F13/372 , G06F12/00 , G06F12/08 , G06F13/14 , G06F13/364 , G06F13/368
CPC分类号： G06F13/364 , G06F12/0846
摘要： A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.
摘要翻译：用于管理多循环数据传输请求的分布式仲裁的方法和系统在处理系统中提供改善的性能。多周期请求指示符被提供给切片仲裁器，并且如果存在多周期请求，则只有一个切片被授予其相关联的总线。该方法进一步阻止来自具有比第一片低的等待时间的其他请求片的任何请求，直到其他请求片之间的等待时间差与添加到预定周期计数值的最长等待时间片已经期满为止。该方法还阻止来自第一片的进一步请求，直到经过了预定周期计数器值，并且阻止来自具有比第一片的更高等待时间的片的请求，直到预定周期计数值减去第一片的延迟差和较高延迟片已过。

26. 发明授权

US09065840B2 Determining server write activity levels to use to adjust write cache size 有权
标题翻译：确定用于调整写缓存大小的服务器写入活动级别
公开(公告)号：US09065840B2
公开(公告)日：2015-06-23
申请号：US13478868
申请日：2012-05-23
申请人： Robert H. Bell, Jr. , Michael D. Roll , Olga Yiparaki
发明人： Robert H. Bell, Jr. , Michael D. Roll , Olga Yiparaki
IPC分类号： G06F12/00 , H04L29/08 , G06F11/34
CPC分类号： H04L67/1097 , G06F11/3409 , G06F11/3442 , G06F11/3485 , G06F2201/81 , G06F2201/88 , G06F2201/885 , H04L67/2847 , H04L67/2852 , H04L67/34 , Y02D10/34
摘要： Provided are a computer program product, system, and method for determining server write activity levels to use to adjust write cache size. Information on server write activity to the cache is gathered. The gathered information on write activity is processed to determine a server write activity level comprising one of multiple write activity levels indicating a level of write activity. The determined server write activity level is transmitted to a storage server having a write cache, wherein the storage server uses the determined server write activity level to determine whether to adjust a size of the storage server write cache.
摘要翻译：提供了一种用于确定用于调整写入高速缓存大小的服务器写入活动级别的计算机程序产品，系统和方法。收集有关缓存服务器写入活动的信息。处理收集的关于写入活动的信息以确定包括指示写入活动级别的多个写入活动级别中的一个的服务器写入活动级别。确定的服务器写入活动级别被发送到具有写入高速缓存的存储服务器，其中存储服务器使用所确定的服务器写入活动级别来确定是否调整存储服务器写入高速缓存的大小。

27. 发明授权

US08886918B2 Dynamic instruction execution based on transaction priority tagging 有权
标题翻译：基于事务优先级标记的动态指令执行
公开(公告)号：US08886918B2
公开(公告)日：2014-11-11
申请号：US11946504
申请日：2007-11-28
申请人： Louis B. Capps, Jr. , Robert H. Bell, Jr.
发明人： Louis B. Capps, Jr. , Robert H. Bell, Jr.
IPC分类号： G06F9/30 , G06F11/34 , G06F9/50 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/5011 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/885 , G06F2209/507 , Y02D10/22 , Y02D10/34
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将每个线程的分配优先级值作为标签存储在线程的指令中，基于分配给各个指令线程的标记的优先级值来分配来自系统调度的来自不同线程的标记指令。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

28. 发明授权

US08645673B2 Multicore processor and method of use that adapts core functions based on workload execution 失效
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08645673B2
公开(公告)日：2014-02-04
申请号：US13613936
申请日：2012-09-13
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/06 , G06F9/24
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

29. 发明授权

US08544006B2 Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict 有权
标题翻译：通过在发生冲突后由主要组件生成的寄存器和内存值重新启动失败的离散可执行子组件的执行来解决冲突
公开(公告)号：US08544006B2
公开(公告)日：2013-09-24
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

30. 发明授权

US08527997B2 Energy-aware job scheduling for cluster environments 失效
公开(公告)号：US08527997B2
公开(公告)日：2013-09-03
申请号：US13458860
申请日：2012-04-27
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
IPC分类号： G06F9/46 , G06F1/26
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A job scheduler can select a processor core operating frequency for a node in a cluster to perform a job based on energy usage and performance data. After a job request is received, an energy aware job scheduler accesses data that specifies energy usage and job performance metrics that correspond to the requested job and a plurality of processor core operating frequencies. A first of the plurality of processor core operating frequencies is selected that satisfies an energy usage criterion for performing the job based, at least in part, on the data that specifies energy usage and job performance metrics that correspond to the job. The job is assigned to be performed by a node in the cluster at the selected first of the plurality of processor core operating frequencies.

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