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21. 发明申请

US20060026321A1 Increasing the number of I/O decode ranges using SMI traps 有权
标题翻译：使用SMI陷阱增加I / O解码范围的数量
公开(公告)号：US20060026321A1
公开(公告)日：2006-02-02
申请号：US10909657
申请日：2004-08-02
申请人： Madhusudhan Rangarajan , Saurabh Gupta
发明人： Madhusudhan Rangarajan , Saurabh Gupta
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset including generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap. The I/O address operably received at the chipset via a bus. The method further including automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus.
摘要翻译：公开了一种使用系统管理中断（SMI）陷阱来增加输入/输出（I / O）解码范围的方法。在一方面，本公开教导了一种使用芯片组中的SMI陷阱来增加I / O解码范围的数量的方法，包括基于引起对触发SMI的I / O地址的访问的信息来生成系统管理中断（SMI）陷阱。通过总线在芯片组可操作地接收的I / O地址。该方法还包括自动重新编程芯片组中的解码寄存器，使得I / O地址将信息转发到总线上的设备。

22. 发明授权

US08078890B2 System and method for providing memory performance states in a computing system 有权
标题翻译：用于在计算系统中提供存储器性能状态的系统和方法
公开(公告)号：US08078890B2
公开(公告)日：2011-12-13
申请号：US11853255
申请日：2007-09-11
申请人： Vijay Nijhawan , Madhusudhan Rangarajan
发明人： Vijay Nijhawan , Madhusudhan Rangarajan
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F13/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A system and method is disclosed for providing memory performance states in a computing system. The operating system power management component of the computing system establishes a set of performance states, with each performance state being defined by a number of factors, including the core frequency of memory. The operating system power management component also defines the number of memory performance states that are supported by the computing system and the number of supported memory performance states that are available for use by the computing system. Whether a supported memory performance state is available is dependent upon a measure of the power being consumed by the computing system, the thermal output of the computing system, or both measures.
摘要翻译：公开了一种用于在计算系统中提供存储器性能状态的系统和方法。计算系统的操作系统电源管理组件建立一组性能状态，每个性能状态由许多因素定义，包括存储器的核心频率。操作系统电源管理组件还定义了计算系统支持的内存性能状态数量以及可供计算系统使用的支持的内存性能状态数。支持的存储器性能状态是否可用取决于计算系统消耗的功率的度量，计算系统的热输出或两种测量。

23. 发明授权

US07921266B2 System and method of accessing memory within an information handling system 有权
标题翻译：在信息处理系统中访问存储器的系统和方法
公开(公告)号：US07921266B2
公开(公告)日：2011-04-05
申请号：US12021755
申请日：2008-01-29
申请人： Madhusudhan Rangarajan , Bi-Chong Wang
发明人： Madhusudhan Rangarajan , Bi-Chong Wang
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor.
摘要翻译：公开了一种在信息处理系统内访问存储器的系统和方法。在一种形式中，访问存储器的方法可以包括检测第一处理器可访问的第一存储器访问节点的第一操作值，以及启动第一存储器访问节点的操作为第一数据速率值。该方法还可以包括启动第二存储器访问节点到第二数据速率值的操作。在一种形式中，第二数据速率值可以不同于第一数据速率值。该方法还可以包括通过由处理器启用的操作系统来启用第一应用程序访问第一存储器访问节点或第二存储器访问节点。

24. 发明授权

US07797473B2 System for executing system management interrupts and methods thereof 有权
标题翻译：用于执行系统管理中断的系统及其方法
公开(公告)号：US07797473B2
公开(公告)日：2010-09-14
申请号：US12133580
申请日：2008-06-05
申请人： Madhusudhan Rangarajan , Vijay Nijhawan
发明人： Madhusudhan Rangarajan , Vijay Nijhawan
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler, a second processor device of the information handling system can continue to execute software and perform other operations in a normal mode. When the first processor device accesses a shared resource in executing the SMI handler, an SMI trap for the shared resource is enabled. In response to the second processor device triggering the SMI trap by accessing the shared resource, the second processor device enters an SMI mode, thereby suspending execution of software and other operations. Accordingly, a second processor device is allowed to continue normal operations while a first processor device executes an SMI handler, improving system efficiency while preventing shared resource conflicts.
摘要翻译：信息处理系统包括响应于系统管理中断（SMI）来执行处理程序的第一处理器设备。当第一处理器设备执行SMI处理程序时，信息处理系统的第二处理器设备可以继续执行软件并以正常模式执行其他操作。当第一个处理器设备在执行SMI处理程序时访问共享资源时，会启用共享资源的SMI陷阱。响应于通过访问共享资源来触发SMI陷阱的第二处理器设备，第二处理器设备进入SMI模式，从而暂停执行软件和其他操作。因此，允许第二处理器设备继续正常操作，同时第一处理器设备执行SMI处理程序，提高系统效率同时防止共享资源冲突。

25. 发明申请

US20080082711A1 System and method for managing system management interrupts in a multiprocessor computer system 有权
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082711A1
公开(公告)日：2008-04-03
申请号：US11540805
申请日：2006-09-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译：公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。主处理器将识别系统管理中断的启动。主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。如果是这样，系统管理中断由本地处理器处理。在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。

26. 发明申请

US20080028117A1 Method and Apparatus for Notifying User About Non-Optimal Hot-Add Memory Configurations 审中-公开
标题翻译：用于通知用户关于非最佳热添加存储器配置的方法和装置
公开(公告)号：US20080028117A1
公开(公告)日：2008-01-31
申请号：US11460056
申请日：2006-07-26
申请人： Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/06 , G06F13/4081 , G06F2212/1016
摘要： During power-on self-test (POST) the basic input-output operating system (BIOS) may set hot-add status light emitting diodes (LEDs) to appropriate colors so as to indicate which memory slot(s) is most optimal for hot-adding a hot-plug memory module. In the case where the user or administrator fails to notice or understand the meaning of the LED color representation when hot-adding the new memory module, the BIOS Service Management Initiative (SMI) handler (which controls the hot-add to the information handling system) will verify if the hot-add memory module is being installed into an optimal memory slot. If not, the BIOS may capture a Chassis System Event Log (SEL) indicating a non-optimal Hot-add and may flash a front panel LED to a certain color, e.g., amber, and may also issue an appropriate error message. Additional Advanced Configuration and Power Interface (ACPI) implementations may be used for a more user-friendly alert and/or message display.
摘要翻译：在开机自检（POST）期间，基本输入输出操作系统（BIOS）可以将热添加状态发光二极管（LED）设置为适当的颜色，以指示哪些内存插槽最适合热 - 添加热插拔内存模块。在热添加新内存模块时，用户或管理员无法注意或了解LED颜色表示的含义的情况下，BIOS服务管理计划（SMI）处理程序（其控制热添加到信息处理系统）将验证热添加内存模块是否正在安装到最佳内存插槽中。如果没有，则BIOS可能会捕获指示非最佳热添加的底盘系统事件日志（SEL），并可能会将前面板LED闪烁到某种颜色（例如琥珀色），并且还可能会发出适当的错误消息。附加的高级配置和电源接口（ACPI）实现可以用于更加用户友好的警报和/或消息显示。

27. 发明申请

US20070233967A1 Optimized memory allocator for a multiprocessor computer system 有权
标题翻译：针对多处理器计算机系统的优化内存分配器
公开(公告)号：US20070233967A1
公开(公告)日：2007-10-04
申请号：US11392272
申请日：2006-03-29
申请人： Madhusudhan Rangarajan , Vijay Nijhawan
发明人： Madhusudhan Rangarajan , Vijay Nijhawan
IPC分类号： G06F12/00
CPC分类号： G06F12/0646 , G06F12/0806 , G06F2212/2542
摘要： The present disclosure describes systems and methods for allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distribute shared memory. The systems and methods include allocating memory to input-output devices (I/O devices) based at least in part on which memory resource is physically closest to a particular I/O device. Through these systems and methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory to an I/O device that i80s on the same node as a memory resource, reduces memory access time thereby maximizing data transmission. The present disclosure further describes a system and method for improving performance in a multiprocessor computer system by utilizing a pre-programmed device affinity table. The system and method includes listing the memory resources physically closest to each I/O device and accessing the device table to determine the closest memory resource to a particular I/O device. The system and method further includes directing a device driver to transmit data between the I/O device and the closest memory resource.
摘要翻译：本公开描述了在诸如具有分发共享存储器的不均匀存储器访问（NUMA）机器的多处理器计算机系统中分配存储器的系统和方法。所述系统和方法包括至少部分地基于哪个存储器资源物理上最接近于特定I / O设备而将存储器分配给输入输出设备（I / O设备）。通过这些系统和方法，在NUMA机器中更有效地分配存储器。例如，将内存分配给与存储器资源相同的节点上的i80的I / O设备，从而减少存储器访问时间，从而最大化数据传输。本公开进一步描述了通过利用预编程的设备亲和度表来改善多处理器计算机系统中的性能的系统和方法。系统和方法包括列出物理上最接近每个I / O设备的存储器资源并访问设备表以确定到特定I / O设备的最近的存储器资源。该系统和方法还包括引导设备驱动器在I / O设备和最接近的存储器资源之间传输数据。

28. 发明授权

US07225284B2 Increasing the quantity of I/O decode ranges using SMI traps 有权
标题翻译：使用SMI陷阱增加I / O解码范围的数量
公开(公告)号：US07225284B2
公开(公告)日：2007-05-29
申请号：US10909657
申请日：2004-08-02
申请人： Madhusudhan Rangarajan , Saurabh Gupta
发明人： Madhusudhan Rangarajan , Saurabh Gupta
IPC分类号： G06F13/00 , G06F13/24 , G06F13/36 , G06F13/12
CPC分类号： G06F13/24
摘要： A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset including generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap. The I/O address operably received at the chipset via a bus. The method further including automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus.
摘要翻译：公开了一种使用系统管理中断（SMI）陷阱来增加输入/输出（I / O）解码范围的方法。在一方面，本公开教导了一种使用芯片组中的SMI陷阱来增加I / O解码范围的数量的方法，包括基于引起对触发SMI的I / O地址的访问的信息来生成系统管理中断（SMI）陷阱。通过总线在芯片组可操作地接收的I / O地址。该方法还包括自动重新编程芯片组中的解码寄存器，使得I / O地址将信息转发到总线上的设备。

29. 发明授权

US09110716B2 Information handling system power management device and methods thereof 有权
标题翻译：信息处理系统电源管理装置及其方法
公开(公告)号：US09110716B2
公开(公告)日：2015-08-18
申请号：US12136518
申请日：2008-06-10
申请人： Mukund P. Khatri , Vijay Nijhawan , Dirie N. Herzi , Madhusudhan Rangarajan
发明人： Mukund P. Khatri , Vijay Nijhawan , Dirie N. Herzi , Madhusudhan Rangarajan
IPC分类号： G06F9/30 , G06F9/48 , G06F1/32
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/329 , G06F2209/483 , Y02D10/126 , Y02D10/24
摘要： An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.
摘要翻译：信息处理系统包括一组功率和性能特征。基于哪个配置文件被选择，信息处理系统选择线程调度表来提供给操作系统。线程调度表确定程序线程被调度执行的处理器核心的顺序。在省电模式中，对应的线程调度表提供线程集中在可用处理器核心的子集上，从而增加信息处理系统可以将未使用的处理器置于降低功率状态的频率。

30. 发明授权

US08359386B2 System and method of migrating virtualized environments 有权
标题翻译：迁移虚拟化环境的系统和方法
公开(公告)号：US08359386B2
公开(公告)日：2013-01-22
申请号：US12425094
申请日：2009-04-16
申请人： Vaden A. Mohrmann , Madhusudhan Rangarajan
发明人： Vaden A. Mohrmann , Madhusudhan Rangarajan
IPC分类号： G06F11/30
CPC分类号： H04L63/10 , G06F21/53 , G06F21/57
摘要： A system and method migrating virtualized environments is disclosed. According to an aspect of the disclosure, the information handling system can include a migration monitor configured to initiate migration of a remote virtualized environment operating on a first remote system. The information handling system can also include a trusted platform module including a local memory storing a plurality of access keys configured to enable use of a plurality of virtualized environments. According to an aspect, the plurality of access keys can include a first access key configured to be used with a first remote system. The information handling system can also include a secure communication channel configured to enable a mapping of the first access key to a second remote system upon the migration monitoring determining the second remote system is capable of satisfying an operating characteristic of the remote virtualized environment.
摘要翻译：公开了一种迁移虚拟化环境的系统和方法。根据本公开的一个方面，信息处理系统可以包括被配置为启动在第一远程系统上操作的远程虚拟化环境的迁移的迁移监视器。信息处理系统还可以包括可信平台模块，其包括存储多个访问密钥的本地存储器，所述多个访问密钥被配置为能够使用多个虚拟化环境。根据一个方面，多个访问密钥可以包括被配置为与第一远程系统一起使用的第一访问密钥。信息处理系统还可以包括安全通信通道，其被配置为在迁移监视确定第二远程系统能够满足远程虚拟化环境的操作特性时能够将第一访问密钥映射到第二远程系统。

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