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1. 发明申请

US20110283286A1 Methods and systems for dynamically adjusting performance states of a processor 审中-公开
标题翻译：用于动态调整处理器性能状态的方法和系统
公开(公告)号：US20110283286A1
公开(公告)日：2011-11-17
申请号：US12800192
申请日：2010-05-11
申请人： Wuxian Wu , Dirie N. Herzi , Gregory N. Darnell , Vijay Nijhawan
发明人： Wuxian Wu , Dirie N. Herzi , Gregory N. Darnell , Vijay Nijhawan
IPC分类号： G06F9/46
CPC分类号： G06F1/329 , Y02D10/24
摘要： A method for dynamically adjusting performance states of a processor includes executing a workload associated with a workload mode and determining a primary thread among all processor threads executing the workload. The method also includes calculating and setting a performance state (P state) of the processor based on the workload mode.
摘要翻译：用于动态调整处理器的性能状态的方法包括执行与工作负载模式相关联的工作负载，并确定执行工作负载的所有处理器线程中的主线程。该方法还包括基于工作负载模式来计算和设置处理器的性能状态（P状态）。

2. 发明授权

US06640316B1 Boot recovery of simple boot BIOS 有权
标题翻译：引导恢复简单的启动BIOS
公开(公告)号：US06640316B1
公开(公告)日：2003-10-28
申请号：US09577025
申请日：2000-05-23
申请人： Todd R. Martin , Dirie N. Herzi
发明人： Todd R. Martin , Dirie N. Herzi
IPC分类号： G06F1100
CPC分类号： G06F11/1417
摘要： A method, computer system, and apparatus perform a modified simple boot. Rather than following Ver. 1 of the Simple Boot Flag Specification, the simple boot flag is ignored if certain platform corruption errors are detected by the BIOS. When the simple boot flag is set, the BIOS runs through a set of core diagnostics to determine whether a platform corruption has occurred. If BIOS detects that the simple boot flag is set and that no platform corruptions have occurred, then a simple boot is performed. However, if a platform corruption is detected, the set simple boot flag is ignored and a full suite of diagnostics routines is performed by the BIOS during the boot process.
摘要翻译：方法，计算机系统和装置执行修改的简单引导。而不是遵循Ver。 1的简单引导标志规范，如果BIOS检测到某些平台损坏错误，则忽略简单引导标志。当设置简单的启动标志时，BIOS将运行一组核心诊断程序，以确定是否发生了平台损坏。如果BIOS检测到设置了简单的引导标志，并且没有发生平台损坏，则执行简单的引导。但是，如果检测到平台损坏，则设置的简单引导标志将被忽略，并且BIOS在启动过程中将执行一整套诊断程序。

3. 发明授权

US09110716B2 Information handling system power management device and methods thereof 有权
标题翻译：信息处理系统电源管理装置及其方法
公开(公告)号：US09110716B2
公开(公告)日：2015-08-18
申请号：US12136518
申请日：2008-06-10
申请人： Mukund P. Khatri , Vijay Nijhawan , Dirie N. Herzi , Madhusudhan Rangarajan
发明人： Mukund P. Khatri , Vijay Nijhawan , Dirie N. Herzi , Madhusudhan Rangarajan
IPC分类号： G06F9/30 , G06F9/48 , G06F1/32
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/329 , G06F2209/483 , Y02D10/126 , Y02D10/24
摘要： An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.
摘要翻译：信息处理系统包括一组功率和性能特征。基于哪个配置文件被选择，信息处理系统选择线程调度表来提供给操作系统。线程调度表确定程序线程被调度执行的处理器核心的顺序。在省电模式中，对应的线程调度表提供线程集中在可用处理器核心的子集上，从而增加信息处理系统可以将未使用的处理器置于降低功率状态的频率。

4. 发明授权

US07991933B2 Synchronizing processors when entering system management mode 有权
标题翻译：进入系统管理模式时同步处理器
公开(公告)号：US07991933B2
公开(公告)日：2011-08-02
申请号：US12145570
申请日：2008-06-25
申请人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
发明人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
IPC分类号： G06F13/24 , G06F1/12
CPC分类号： G06F13/24 , G06F13/385
摘要： A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.
摘要翻译：同步处理器的系统包括用于接收中断命令的一个或多个子系统，指示多个处理器进入中断处理程序的条目同步循环，由多个处理器中的每一个确定所有多个处理器是否已经进入其中相应的中断处理程序在退出条目同步循环之前，确定是否达到超时值，确定接收到的中断命令的类型，并响应接收的中断命令的类型，并确定是否在超时值后退出条目同步循环已经到达

5. 发明授权

US08260995B2 Processor interrupt command response system 有权
标题翻译：处理器中断命令响应系统
公开(公告)号：US08260995B2
公开(公告)日：2012-09-04
申请号：US13178050
申请日：2011-07-07
申请人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
发明人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
IPC分类号： G06F13/24 , G06F1/12
CPC分类号： G06F13/24 , G06F13/385
摘要： A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.
摘要翻译：同步处理器的系统包括用于接收中断命令的一个或多个子系统，指示多个处理器进入中断处理程序的条目同步循环，由多个处理器中的每一个确定所有多个处理器是否已经进入其中相应的中断处理程序在退出条目同步循环之前，确定是否达到超时值，确定接收到的中断命令的类型，并响应接收到的中断命令的类型，确定超时值是否退出条目同步循环已经到达

6. 发明申请

US20110264837A1 SYNCHRONIZING PROCESSORS WHEN ENTERING SYSTEM MANAGEMENT MODE 有权
标题翻译：进入系统管理模式时同步处理器
公开(公告)号：US20110264837A1
公开(公告)日：2011-10-27
申请号：US13178050
申请日：2011-07-07
申请人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
发明人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F13/385
摘要： A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.
摘要翻译：同步处理器的系统包括用于接收中断命令的一个或多个子系统，指示多个处理器进入中断处理程序的条目同步循环，由多个处理器中的每一个确定所有多个处理器是否已经进入其中相应的中断处理程序在退出条目同步循环之前，确定是否达到超时值，确定接收到的中断命令的类型，并响应接收到的中断命令的类型，确定超时值是否退出条目同步循环已经到达

7. 发明申请

US20090327554A1 SYNCHRONIZING PROCESSORS WHEN ENTERING SYSTEM MANAGEMENT MODE 有权
标题翻译：进入系统管理模式时同步处理器
公开(公告)号：US20090327554A1
公开(公告)日：2009-12-31
申请号：US12145570
申请日：2008-06-25
申请人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
发明人： Juan Francisco Diaz , Dirie N. Herzi , Robert Volentine
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F13/385
摘要： A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.
摘要翻译：同步处理器的系统包括用于接收中断命令的一个或多个子系统，指示多个处理器进入中断处理程序的条目同步循环，由多个处理器中的每一个确定所有多个处理器是否已经进入其中相应的中断处理程序在退出条目同步循环之前，确定是否达到超时值，确定接收到的中断命令的类型，并响应接收到的中断命令的类型，并确定是否在超时值后退出条目同步循环已经到达

8. 发明授权

US06615288B1 Generating system management interrupt in response to usb controller signal and processing interrupt routine in upper most level of system memory 有权
标题翻译：响应于usb控制器信号产生系统管理中断，并处理系统内存最上层的中断程序
公开(公告)号：US06615288B1
公开(公告)日：2003-09-02
申请号：US09472863
申请日：1999-12-27
申请人： Dirie N. Herzi
发明人： Dirie N. Herzi
IPC分类号： G06F1300
CPC分类号： G06F13/24
摘要： Systems and methods for enabling computer system devices and components are disclosed. A method for use in a computer system having a processor includes receiving an input from a device coupled to the system and generating an interrupt signal in response to the input. The method further includes placing the system in a management mode in response to the interrupt and processing an interrupt routine associated with the interrupt. The method further includes processing the interrupt routine located in an upper level of the system's available memory and providing information to a driver associated with the system.
摘要翻译：公开了用于实现计算机系统设备和组件的系统和方法。一种在具有处理器的计算机系统中使用的方法，包括从耦合到系统的设备接收输入并响应于输入产生中断信号。该方法还包括将系统置于响应于中断的管理模式并处理与中断相关联的中断例程。该方法还包括处理位于系统可用存储器的较高级别的中断程序，并向与系统相关联的驱动程序提供信息。

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