专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06467017B1 Programmable logic device having embedded dual-port random access memory configurable as single-port memory 失效
标题翻译：具有可配置为单端口存储器的嵌入式双端口随机存取存储器的可编程逻辑器件
公开(公告)号：US06467017B1
公开(公告)日：2002-10-15
申请号：US09124649
申请日：1998-07-29
申请人： Tony K. Ngai , Rakesh H. Patel , Srinivas T. Reddy , Richard G. Cliff
发明人： Tony K. Ngai , Rakesh H. Patel , Srinivas T. Reddy , Richard G. Cliff
IPC分类号： G06F1200
CPC分类号： H03K19/1776 , G11C7/1075 , G11C2207/104 , H03K19/17736
摘要： A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated programmable interconnection resources. The programmable interconnection resources are arranged so that each pair of corresponding read address and write address inputs can be connected to at least one conductor in common on the conductor bus, allowing the RAM to be configured to mimic a single-port RAM as read address signals and write address signals originating at remote components of the programmable logic device “think” they are being directed to the same address inputs.
摘要翻译：可编程逻辑器件具有嵌入式随机存取存储器（“RAM”），其可在单端口或双端口操作中同等功能。 RAM是双端口RAM，其读地址输入和写地址输入都通过两个不同的稀疏布置的可编程互连资源连接到导体总线。可编程互连资源被布置为使得每对相应的读取地址和写入地址输入可以在导体总线上共同连接到至少一个导体，从而允许RAM被配置为模拟单端口RAM作为读取地址信号并且写入源自可编程逻辑器件的远程组件的地址信号“认为”它们被引导到相同的地址输入。

22. 发明授权

US06392954B2 Dual port programmable logic device variable depth and width memory array 有权
标题翻译：双端口可编程逻辑器件可变深度和宽度存储器阵列
公开(公告)号：US06392954B2
公开(公告)日：2002-05-21
申请号：US09747191
申请日：2000-12-21
申请人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
发明人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
IPC分类号： G11C800
CPC分类号： G11C7/1006
摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.
摘要翻译：提供了双端口可编程逻辑器件存储器阵列。可选择大小的数据字可以并行写入阵列并从阵列中读取。使用写列解码器和数据选择逻辑将数据写入阵列。由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。使用读列解码器和数据选择逻辑从数组中读取数据。由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

23. 发明授权

US06323677B1 Programmable logic device circuitry for improving multiplier speed and/or efficiency 有权
标题翻译：可编程逻辑器件电路，用于提高乘法器速度和/或效率
公开(公告)号：US06323677B1
公开(公告)日：2001-11-27
申请号：US09542211
申请日：2000-04-04
申请人： Christopher F. Lane , Srinivas T. Reddy , Richard G. Cliff , Ketan H. Zaveri , Bruce B. Pedersen , Kerry Veenstra
发明人： Christopher F. Lane , Srinivas T. Reddy , Richard G. Cliff , Ketan H. Zaveri , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H03K19173
CPC分类号： H03K19/17792 , H03K19/17728 , H03K19/17732
摘要： In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.
摘要翻译：为了便于可编程逻辑器件中的乘法性能，这些器件的各个逻辑模块被构造成使得一个逻辑模块可以执行（至少）二进制乘法的一个位置和完全二进制加法的一个位置。这使得可以减少执行乘法所需的逻辑模块的数量。它还减少了乘法中使用的模块间连接的数量，从而倾向于减少执行乘法所需的时间。

24. 发明授权

US06184705B2 Techniques for programming programmable logic array devices 失效
公开(公告)号：US06184705B2
公开(公告)日：2001-02-06
申请号：US08982964
申请日：1997-12-02
申请人： Richard G. Cliff , Srinivas T. Reddy , Andreas Papaliolios
发明人： Richard G. Cliff , Srinivas T. Reddy , Andreas Papaliolios
IPC分类号： H03K19173
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

25. 发明授权

US6052327A Dual-port programmable logic device variable depth and width memory array 失效
标题翻译：双端口可编程逻辑器件可变深度和宽度存储器阵列
公开(公告)号：US6052327A
公开(公告)日：2000-04-18
申请号：US107533
申请日：1998-06-30
申请人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
发明人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
IPC分类号： G11C11/41 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1006
摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.
摘要翻译：提供了双端口可编程逻辑器件存储器阵列。可选择大小的数据字可以并行写入阵列并从阵列中读取。使用写列解码器和数据选择逻辑将数据写入阵列。由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。使用读列解码器和数据选择逻辑从数组中读取数据。由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

26. 发明授权

US6049225A Input/output interface circuitry for programmable logic array integrated circuit devices 失效
标题翻译：用于可编程逻辑阵列集成电路器件的输入/输出接口电路
公开(公告)号：US6049225A
公开(公告)日：2000-04-11
申请号：US23369
申请日：1998-02-13
申请人： Joseph Huang , Richard G. Cliff , Srinivas T. Reddy
发明人： Joseph Huang , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.
摘要翻译：在可编程逻辑阵列集成电路器件中，使用各种技术来增加器件的核心逻辑可以连接到器件的输入和/或输出引脚的灵活性。虽然显示的技术大大增加了电路灵活性，但它们避免了完全一般的不必要的互连开销。

27. 发明授权

US5963049A Programmable logic array integrated circuit architectures 失效
公开(公告)号：US5963049A
公开(公告)日：1999-10-05
申请号：US807561
申请日：1997-02-28
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

28. 发明授权

US5847617A Variable-path-length voltage-controlled oscillator circuit 失效
标题翻译：可变路径长度压控振荡器电路
公开(公告)号：US5847617A
公开(公告)日：1998-12-08
申请号：US909337
申请日：1997-08-11
申请人： Srinivas T. Reddy , David Edward Jefferson , Richard G. Cliff , Cameron McClintock
发明人： Srinivas T. Reddy , David Edward Jefferson , Richard G. Cliff , Cameron McClintock
IPC分类号： H03K3/03 , H03L7/099 , H03B5/24
CPC分类号： H03L7/0997 , H03K3/0315
摘要： A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.
摘要翻译：提供了可变路径长度的压控振荡器电路。振荡器电路具有由一系列压控逆变器级形成的环形振荡器。基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。所选择的路径长度决定了环形振荡器的额定或中心频率。通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。

29. 发明授权

US06191608B1 Techniques for programming programmable logic array devices 失效
标题翻译：用于编程可编程逻辑阵列器件的技术
公开(公告)号：US06191608B1
公开(公告)日：2001-02-20
申请号：US08851250
申请日：1997-05-05
申请人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
发明人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
IPC分类号： H03K19177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译：可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。可以使用几个并行数据流来加速编程操作。可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

30. 发明授权

US5986470A Programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US5986470A
公开(公告)日：1999-11-16
申请号：US970830
申请日：1997-11-14
申请人： Richard G. Cliff , Srinivas T. Reddy , Rina Raman , L. Todd Cope , Joseph Huang , Bruce B. Pedersen
发明人： Richard G. Cliff , Srinivas T. Reddy , Rina Raman , L. Todd Cope , Joseph Huang , Bruce B. Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式