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21. 发明授权

US08148787B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08148787B2
公开(公告)日：2012-04-03
申请号：US12719952
申请日：2010-03-09
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

22. 发明授权

US08129792B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08129792B2
公开(公告)日：2012-03-06
申请号：US12233055
申请日：2008-09-18
申请人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.
摘要翻译：半导体器件包括分别形成在衬底上的n型和p型半导体区，形成在衬底上的层间绝缘体，并且具有形成为达到n型和p型区的第一和第二沟槽。还包括形成在第一和第二沟槽内的第一和第二栅极绝缘体，经由第一栅极绝缘体形成在第一沟槽内部的第一金属层，形成为厚度为1单层或更多和1.5nm的第二金属层或更少的内部经由所述第二栅极绝缘体，形成在所述第二金属层上并且包含至少一种碱土金属元素的单质，氮化物，碳化物和氧化物中的至少一种的第三金属层金属元素和III族元素，形成在n型和p型区上的第一和第二源/漏区。

23. 发明申请

US20120049289A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120049289A1
公开(公告)日：2012-03-01
申请号：US13290552
申请日：2011-11-07
申请人： Reika ICHIHARA , Masato Koyama
发明人： Reika ICHIHARA , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

24. 发明授权

US07863695B2 Complementary MISFET semiconductor device having an atomic density ratio aluminum/lanthanum (Al/La) in the gate insulating layer of PMIS is larger than that of the NMIS 有权
标题翻译：在PMIS的栅极绝缘层中具有铝/镧原子密度比（Al / La）的互补MISFET半导体器件大于NMIS
公开(公告)号：US07863695B2
公开(公告)日：2011-01-04
申请号：US12200599
申请日：2008-08-28
申请人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
发明人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/26506 , H01L21/31155 , H01L21/823842 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7842 , H01L29/7846 , H01L29/785
摘要： A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.
摘要翻译：互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管，以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

25. 发明申请

US20090317951A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090317951A1
公开(公告)日：2009-12-24
申请号：US12554339
申请日：2009-09-04
申请人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.
摘要翻译：半导体器件在衬底上具有n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在基板上的p型半导体区域，通过p型半导体区域上方的栅极绝缘膜形成并且为单层以上且3nm以下的下层栅电极以及形成在下层栅电极上的上层栅电极，其平均电负性比下层栅电极的平均电负性小0.1或更小。 p沟道MIS晶体管包括形成在衬底上的n型半导体区域和通过n型半导体区域上方的栅极绝缘膜形成并由与上层相同的金属材料制成的栅电极栅电极。

26. 发明授权

US07612413B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07612413B2
公开(公告)日：2009-11-03
申请号：US11461646
申请日：2006-08-01
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823835
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.
摘要翻译：半导体器件包括衬底，形成在衬底上的p沟道MIS晶体管，具有第一栅电极的p沟道MIS晶体管和与p沟道MIS晶体管分开形成在衬底上的n沟道MIS晶体管，该n沟道MIS晶体管具有第二栅电极。第一栅极电极和第二栅极电极由Ta和C的合金形成，其中C与Ta（C / Ta）的摩尔比为2〜4。

27. 发明授权

US07563678B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07563678B2
公开(公告)日：2009-07-21
申请号：US11812839
申请日：2007-06-22
申请人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.

28. 发明授权

US07541657B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07541657B2
公开(公告)日：2009-06-02
申请号：US12133583
申请日：2008-06-05
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

29. 发明申请

US20070249106A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070249106A1
公开(公告)日：2007-10-25
申请号：US11812839
申请日：2007-06-22
申请人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.
摘要翻译：可以提供一种包括具有门电极的CMOS器件的半导体器件，其中阈值电压的变化很小。存在设置在半导体衬底中的p沟道MIS晶体管和n沟道MIS晶体管，并且在p沟道MIS晶体管的栅电极的区域中，除了与栅极绝缘膜，氧浓度为10〜30厘米-3以上且10〜22厘米-3以上或减。

30. 发明申请

US20060180870A1 Semiconductor device 有权
公开(公告)号：US20060180870A1
公开(公告)日：2006-08-17
申请号：US11299773
申请日：2005-12-13
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

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