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21. 发明授权

US06633967B1 Coherent translation look-aside buffer 有权
标题翻译：相干翻译后备缓冲区
公开(公告)号：US06633967B1
公开(公告)日：2003-10-14
申请号：US09652985
申请日：2000-08-31
申请人： Samuel H. Duncan
发明人： Samuel H. Duncan
IPC分类号： G06F1200
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/682
摘要： The invention is a coherent translation look-aside buffer (TLB) for use in an input/output (I/O) bridge of a symmetrical multiprocessing (SMP) system. The contents of the TLBs may be kept in one of two possible states: exclusive or invalid. When the I/O bridge receives a TLB entry for storage in its TLB, the state of that entry is exclusive. Specifically, the TLB is considered the exclusive owner of the respective TLB entry. The exclusively owned TLB entry may be used by the TLB to translate I/O addresses to system addresses. If some other agent or entity of the SMP system seeks access to the TLB entry (e.g., for purposes of executing a read or write operation), the TLB is notified and the state of the TLB entry transitions to invalid. With the TLB entry in the invalid state, the TLB can no longer use the TLB entry for translating I/O addresses to system addresses.
摘要翻译：本发明是用于在对称多处理（SMP）系统的输入/输出（I / O）桥中使用的相干翻译后备缓冲器（TLB）。 TLB的内容可以保持在两种可能的状态之一：独占或无效。当I / O桥接收到TLB中存储的TLB条目时，该条目的状态是排他的。具体来说，TLB被认为是相应TLB条目的排他所有者。 TLB可以使用专有的TLB条目将I / O地址转换为系统地址。如果SMP系统的某些其他代理或实体寻求访问TLB条目（例如，为了执行读或写操作的目的），则通知TLB并且TLB条目的状态转换为无效。在TLB条目处于无效状态时，TLB不能再使用TLB条目将I / O地址转换为系统地址。

22. 发明授权

US5481555A System and method for error detection and reducing simultaneous switching noise 失效
标题翻译：用于错误检测和降低同时开关噪声的系统和方法
公开(公告)号：US5481555A
公开(公告)日：1996-01-02
申请号：US206914
申请日：1994-03-07
申请人： Paul C. Wade , Samuel H. Duncan , Donald W. Smelser
发明人： Paul C. Wade , Samuel H. Duncan , Donald W. Smelser
IPC分类号： G06F11/00 , G06F11/10 , H03K17/16 , H03K19/003 , H03M5/14 , H03M7/00 , H03M7/14 , H03M7/20 , H03M13/00 , H03M13/51 , H04L1/00 , H04L25/02
CPC分类号： H03M5/145 , H03M7/20
摘要： A system and method that reduces the simultaneous switching noise of outputs and the processing delays caused by inductance by using an encoding scheme that results in a net signaling current of substantially zero at each cycle time for the fast parallel switching networks of digital integrated circuit chips and that provides multiple types of error detection.
摘要翻译：一种通过使用编码方案来减少输出的同时开关噪声和由电感引起的处理延迟的系统和方法，所述编码方案导致数字集成电路芯片的快速并行交换网络在每个周期时间内的净信令电流基本为零，它提供了多种类型的错误检测。

23. 发明授权

US08539130B2 Virtual channels for effective packet transfer 有权
标题翻译：用于有效数据包传输的虚拟通道
公开(公告)号：US08539130B2
公开(公告)日：2013-09-17
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

24. 发明申请

US20110072177A1 VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER 有权
标题翻译：用于有效分组传输的虚拟通道
公开(公告)号：US20110072177A1
公开(公告)日：2011-03-24
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

25. 发明申请

US20100153658A1 Deadlock Avoidance By Marking CPU Traffic As Special 有权
标题翻译：通过将CPU流量标记为特殊来防止死锁
公开(公告)号：US20100153658A1
公开(公告)日：2010-06-17
申请号：US12334394
申请日：2008-12-12
申请人： Samuel H. Duncan , David B. Glasco , Wei-je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
发明人： Samuel H. Duncan , David B. Glasco , Wei-je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
IPC分类号： G06F12/08
CPC分类号： G06F13/4221 , G06F9/3877 , G06F13/1663
摘要： Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.
摘要翻译：通过将由并行处理器发出的读取请求标记为系统内存作为“特殊”来避免死锁。读取完成与读取请求相关联，标记为特殊的请求在PCIe总线的虚拟通道1上路由。虚拟通道1上返回的数据不能因虚拟通道0中的写入请求而停止，从而避免潜在的死锁。

26. 发明授权

US06832282B2 System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system 有权
标题翻译：在多处理器计算机系统中提供前进进步和避免饥饿和活动锁定的系统和方法
公开(公告)号：US06832282B2
公开(公告)日：2004-12-14
申请号：US10611569
申请日：2003-07-01
申请人： Samuel H. Duncan , Steven Ho
发明人： Samuel H. Duncan , Steven Ho
IPC分类号： G06F1336
CPC分类号： G06F12/0835
摘要： A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.
摘要翻译：一种系统和方法避免了竞争相同数据的对称多处理器（SMP）计算机系统的两个或多个输入/输出（I / O）设备中的“活动锁定”和“饥饿”。 SMP计算机系统包括多个互连处理器，由处理器共享的一个或多个存储器以及I / O设备耦合到的多个I / O桥。执行缓存一致性协议的I / O网桥，这需要I / O网桥获得由桥接器存储的所有数据的“独占”（非共享）所有权。响应于对I / O桥当前存储的数据的请求，桥接器首先在将数据无效之前将该数据的至少一部分复制到非相干缓冲器。然后，桥接器保存在其非相干缓冲器中的最大数量的数据，其被认为是相干的，并且仅将已知的相干量释放到I / O设备，然后丢弃所有保存的数据。

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