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21. 发明授权

US06516404B1 Data processing system having hashed architected processor facilities 失效
标题翻译：数据处理系统散布了架构化的处理器设备
公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译：具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。

22. 发明授权

US06349367B1 Method and system for communication in which a castout operation is cancelled in response to snoop responses 失效
标题翻译：用于通信的方法和系统，其中响应于窥探响应取消了退出操作
公开(公告)号：US06349367B1
公开(公告)日：2002-02-19
申请号：US09368228
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0804
摘要： An effectively “conditional”, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.
摘要翻译：可以通过对操作的组合的响应来取消有效的“有条件”，丢弃包括相关数据访问在内的组合操作的部分。组合的响应逻辑在窥探者和垂直的在线存储器中接收对应于被丢弃的受害者的高速缓存行的相关性状态和/或LRU位置信息。组合的响应逻辑还可以接收关于在受害者的同余类中的窥探者或低级存储器中存在共享或无效高速缓存行的信息，或者关于数据访问目标的一次读取性质的信息。基于这些响应，组合的响应逻辑确定是否应该取消推出，如果是，则选择并驱动适当的组合响应代码。

23. 发明授权

US06279086B1 Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position 失效
标题翻译：具有组合侦听响应的多处理器系统总线隐式更新snooper LRU位置
公开(公告)号：US06279086B1
公开(公告)日：2001-08-21
申请号：US09368227
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/123
摘要： Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines, from LRU position information appended to the combined response to the combined operation, whether the coherency state and/or LRU position of the victim may be upgraded within the subject storage device. If so, the coherency state or LRU position is upgraded to improve global data storage management. For instance, a cache line within a snooping storage device may be altered to assume the coherency state of the victim within the storage device initiating the combined operation to improve data storage management under a given replacement policy.
摘要翻译：在窥探组合的数据访问并且通过水平存储设备推出/取消分配操作时，窥探逻辑从附加到对组合操作的组合响应的LRU位置信息确定受害者的相关性状态和/或LRU位置是否可以在主题存储设备内进行升级。如果是这样，则一致性状态或LRU位置被升级以改进全局数据存储管理。例如，可以改变窥探存储设备内的高速缓存行，以假定存储设备内的受害者的一致性状态发起组合操作，以改善给定替换策略下的数据存储管理。

24. 发明授权

US06275909B1 Multiprocessor system bus with system controller explicitly updating snooper cache state information 失效
标题翻译：具有系统控制器的多处理器系统总线显式更新窥探缓存状态信息
公开(公告)号：US06275909B1
公开(公告)日：2001-08-14
申请号：US09368226
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0811
摘要： Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy with a coherency state of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state information appended to the combined operation and the snoop responses, whether a coherency upgrade is possible. If so, the combined response logic selects a snooper storage device to upgrade the coherency state of a respective cache line corresponding to the victim, and appends an upgrade directive to the combined response. The snooper selected to upgrade the coherency state of a cache line corresponding the victim may be randomly chosen or, as an optimization, be chosen for having the highest LRU position for the respective cache line.
摘要翻译：总线的组合响应逻辑接收组合的数据访问，并且通过存储分层结构的特定级别中的存储设备发起/撤销分配操作，所述存储层级具有附加的转出/取消分配的受害者的一致性状态。总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。组合响应逻辑从附加到组合操作和窥探响应的一致性状态信息确定是否可以进行一致性升级。如果是这样，组合的响应逻辑选择窥探存储设备来升级与受害者相对应的相应高速缓存行的一致性状态，并且将升级指令附加到组合响应。选择用于升级与受害者相对应的高速缓存线的相关性状态的窥探者可以被随机选择，或者作为优化被选择以具有用于相应高速缓存行的最高LRU位置。

25. 发明授权

US06598118B1 Data processing system with HSA (hashed storage architecture) 失效
标题翻译：具有HSA（散列存储架构）的数据处理系统
公开(公告)号：US06598118B1
公开(公告)日：2003-07-22
申请号：US09364284
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G60F1200
CPC分类号： G06F12/0864
摘要： A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
摘要翻译：具有散列和分区存储子系统的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和包括存储由执行单元使用的数据的多个高速缓存的高速缓存子系统。多个高速缓存中的每个高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关地址的数据。在一个优选实施例中，处理器的执行单元包括多个加载存储单元（LSU），每个加载存储单元仅处理访问在多个地址子集中的相应一个地址子集内具有相关联地址的数据的指令。处理器还可以并入具有多个互连的数据处理系统和多个系统存储器硬件的集合，每个系统存储器硬件各自对多个地址子集中的相应一个具有亲和力。

26. 发明授权

US06477613B1 Cache index based system address bus 有权
标题翻译：基于缓存索引的系统地址总线
公开(公告)号：US06477613B1
公开(公告)日：2002-11-05
申请号：US09345302
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897
摘要： Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin directory lookups in lower level storage devices before the address tag is received. The remainder of the address is transmitted during subsequent bus cycles, which should be in time for address tag comparisons with the congruence class elements. To allow multiple directory lookups to be occurring concurrently in a pipelined directory, a portion of multiple addresses for several data access operations, each portion including the index field for the respective address, may be transmitted during the first bus cycle or staged in consecutive bus cycles, with the remainders of each address—including the cache tags—transmitted during the subsequent bus cycles. This allows directory lookups utilizing the index fields to be processed concurrently within a lower level storage device for multiple operations, with the address tags being provided later, but still timely for tag comparisons at the end of the directory lookup. Where the lower level storage device operates at a higher frequency than the bus, overall latency is reduced and directory bandwidth is more efficiently utilized.
摘要翻译：在操作的高速缓存未命中之后，操作的地址在将高速缓存耦合到存储层级的较低级别的总线上传输。包括索引字段的地址的一部分在第一总线周期期间被发送，并且可以用于在接收到地址标签之前开始下级存储设备中的目录查找。在随后的总线周期期间传送地址的其余部分，这些时间应与地址标签与同余类元素进行比较。为了允许在流水线目录中同时发生多个目录查找，可以在第一个总线周期期间发送多个数据访问操作的多个地址的一部分，每个部分包括相应地址的索引字段，或者在连续的总线周期中分段，每个地址的剩余部分，包括在后续总线周期期间发送的缓存标签。这允许使用索引字段的目录查找在较低级存储设备中同时处理以用于多个操作，其中地址标签稍后提供，但是在目录查找结束时仍然适合于标签比较。在较低级存储设备以比总线更高的频率工作的地方，总体延迟降低，目录带宽更有效地利用。

27. 发明授权

US06343344B1 System bus directory snooping mechanism for read/castout (RCO) address transaction 失效
标题翻译：系统总线事务与缓存标签的受害者地址
公开(公告)号：US06343344B1
公开(公告)日：2002-01-29
申请号：US09368221
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0859
摘要： In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.
摘要翻译：响应于接收到用于相关数据访问和丢弃操作的组合地址，包括标识包含数据访问目标和丢弃的受害者的同余类的索引，使用索引来定位单个目录访问一致类。然后将同余类中的地址标签与用于数据访问操作的地址标签和用于外推操作的地址标签同时进行比较，并酌情生成单独的命中信号。然而，仅需要单个目录访问，而不是如已知技术中所需的两个单独的目录访问，利用数据访问目标和丢弃的受害者都属于单个同余类的事实。响应延迟也得到改善，地址总线带宽利用率也得到提高。

28. 发明授权

US06324617B1 Method and system for communicating tags of data access target and castout victim in a single data transfer 失效
标题翻译：用于在单个数据传输中传送数据访问目标和丢弃受害者的标签的方法和系统
公开(公告)号：US06324617B1
公开(公告)日：2001-11-27
申请号：US09368222
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0859
摘要： A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
摘要翻译：组合的地址总线事务包含用于数据访问操作目标的地址标签，要替换的受害者的地址标签，以及标识包括目标和受害者的一致类的地址索引字段。目的地状态信息，例如用于投放受害者的一致性状态和/或LRU位置也可以附加到总线操作中的索引字段和目标和受害者地址标签。从而改善了地址总线带宽利用率，消除了根据现有实践分离数据访问和丢弃操作所采用的索引字段的重复传输。可以同时确定受害者是否可以在形成组合地址的存储设备内找到目标，从而提高该设备的整体性能。

29. 发明授权

US06801984B2 Imprecise snooping based invalidation mechanism 失效
标题翻译：不精确的基于窥探的无效机制
公开(公告)号：US06801984B2
公开(公告)日：2004-10-05
申请号：US09895119
申请日：2001-06-29
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The directional bits provide information that includes a processor cache identification (ID) and routing method. The processor cache ID indicates which processor's operation resulted in the cache line of the local processor changing to the invalidate (I) coherency state. The routing method indicates what transmission method to utilize to forward the cache line, from among a local system bus or a switch or broadcast mechanism. Processor/Cache directory logic provide responses to requests depending on the values of the directional bits.
摘要翻译：一种方法，系统和处理器高速缓存配置，其能够响应于在本地处理器高速缓存处的无效高速缓存未命中而有效地检索有效数据。除了一致性状态位和地址标签之外，向缓存目录提供一组方向位。方向位提供包括处理器缓存标识（ID）和路由方法的信息。处理器缓存ID指示哪个处理器的操作导致本地处理器的高速缓存行变为无效（I）一致性状态。该路由方法指示用于从本地系统总线或交换机或广播机制中转发高速缓存行的什么传输方法。处理器/缓存目录逻辑根据定向位的值提供对请求的响应。

30. 发明授权

US06470442B1 Processor assigning data to hardware partition based on selectable hash of data address 失效
标题翻译：处理器根据数据地址的可选哈希分配数据到硬件分区
公开(公告)号：US06470442B1
公开(公告)日：2002-10-22
申请号：US09364286
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： B06F1576
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3013 , G06F9/3802 , G06F9/384 , G06F9/3885 , G06F15/7857
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
摘要翻译：处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。执行资源，数据存储和指令排序单元中的至少一个用多个用于处理数据的相同功能的硬件分区来实现。由每个硬件分区处理的数据根据与数据相关联的地址的可选择的散列来分配。在优选实施例中，可以在处理器的操作期间动态地改变可选择的散列，例如响应于硬件分区之间的错误或负载不平衡的检测。

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