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21. 发明申请

US20060211194A1 Methods of reducing floating body effect 有权
公开(公告)号：US20060211194A1
公开(公告)日：2006-09-21
申请号：US11437999
申请日：2006-05-18
申请人： Gordon Haller
发明人： Gordon Haller
IPC分类号： H01L21/8242
CPC分类号： H01L27/0218 , H01L27/10823 , H01L27/10861 , H01L27/10876 , H01L27/10891
摘要： Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

22. 发明申请

US20060046424A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20060046424A1
公开(公告)日：2006-03-02
申请号：US10925789
申请日：2004-08-24
申请人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
发明人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
IPC分类号： H01L21/76
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.
摘要翻译：本发明包括包含垂直延伸柱的半导体结构以及用于形成这种结构的方法。垂直延伸的柱可以并入晶体管器件中，并且可以包含晶体管器件的垂直延伸的沟道区域。晶体管器件可以并入到集成电路中，并且在一些方面被并入存储器结构中，例如动态随机存取存储器（DRAM）结构。

23. 发明申请

US20180108669A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 审中-公开
公开(公告)号：US20180108669A1
公开(公告)日：2018-04-19
申请号：US15296858
申请日：2016-10-18
申请人： Hongbin Zhu , Zhenyu Lu , Gordon Haller , Jie Sun , Randy J. Koval , John Hopkins
发明人： Hongbin Zhu , Zhenyu Lu , Gordon Haller , Jie Sun , Randy J. Koval , John Hopkins
IPC分类号： H01L27/115 , H01L29/10 , H01L29/51 , H01L21/311 , H01L21/28 , H01L21/285
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/28525 , H01L21/28556 , H01L21/31111 , H01L27/1157 , H01L27/11582 , H01L29/1037 , H01L29/513
摘要： Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

24. 发明申请

US20100252886A1 FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES 有权
标题翻译： FIN结构和FIN结构的制作方法
公开(公告)号：US20100252886A1
公开(公告)日：2010-10-07
申请号：US12795495
申请日：2010-06-07
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L27/088 , H01L21/762 , H01L21/28
CPC分类号： H01L29/785 , H01L21/3086 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
摘要翻译：提供了用于制造翅片结构的翅片结构和方法。更具体地，翅片结构形成在基板中。翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

25. 发明授权

US07808053B2 Method, apparatus, and system for flash memory 有权
标题翻译：闪存的方法，设备和系统
公开(公告)号：US07808053B2
公开(公告)日：2010-10-05
申请号：US11618658
申请日：2006-12-29
申请人： Gordon Haller , Luan C. Tran
发明人： Gordon Haller , Luan C. Tran
IPC分类号： H01L27/088
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.
摘要翻译：本发明的实施例提供了包括包括中心区域和外围区域的基板的装置，方法和系统; 在所述基板的表面上方的多个层，在所述多个层的顶表面上的第一多个间距倍数间隔件，所述第一多个间距倍数间隔件在所述基板的中心区域的上方，以及第二多个在所述多个层的顶表面上的间距倍增间隔物，所述第二多个间距倍增间隔物在所述外围区域上方，并且包括至少一个间距倍增间隔物，所述间距倍增间隔物具有距所述至少一个间距倍数间隔物在边界有一个表面。

26. 发明申请

US20100144107A1 Semiconductor Memory Device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100144107A1
公开(公告)日：2010-06-10
申请号：US12703502
申请日：2010-02-10
申请人： Gordon Haller , Sanh Dang Tang , Steve Cummings
发明人： Gordon Haller , Sanh Dang Tang , Steve Cummings
IPC分类号： H01L21/8242
CPC分类号： H01L21/823487 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
摘要翻译：包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

27. 发明申请

US20090311845A1 One Transistor Memory Cell with Bias Gate 有权
标题翻译：一个具有偏置门的晶体管存储单元
公开(公告)号：US20090311845A1
公开(公告)日：2009-12-17
申请号：US12537470
申请日：2009-08-07
申请人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
发明人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
IPC分类号： H01L21/76
CPC分类号： H01L29/7841 , G11C11/401 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10844
摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
摘要翻译：单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子他们在哪里举行。

28. 发明申请

US20080162781A1 METHOD, APPARATUS, AND SYSTEM FOR FLASH MEMORY 有权
标题翻译：闪存存储器的方法，装置和系统
公开(公告)号：US20080162781A1
公开(公告)日：2008-07-03
申请号：US11618658
申请日：2006-12-29
申请人： Gordon Haller , Luan C. Tran
发明人： Gordon Haller , Luan C. Tran
IPC分类号： G11C5/02 , G06F12/00 , H01L21/8239
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.
摘要翻译：本发明的实施例提供了包括包括中心区域和外围区域的基板的装置，方法和系统; 在所述基板的表面上方的多个层，在所述多个层的顶表面上的第一多个间距倍数间隔件，所述第一多个间距倍数间隔件在所述基板的中心区域的上方，以及第二多个在所述多个层的顶表面上的间距倍增间隔物，所述第二多个间距倍增间隔物在所述外围区域上方，并且包括至少一个间距倍增间隔物，所述间距倍增间隔物具有距所述至少一个间距倍数间隔物在边界有一个表面。

29. 发明申请

US20080142882A1 Transistors 有权
标题翻译：晶体管
公开(公告)号：US20080142882A1
公开(公告)日：2008-06-19
申请号：US12070078
申请日：2008-02-15
申请人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen
发明人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen
IPC分类号： H01L29/78
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

30. 发明授权

US07329924B2 Integrated circuits and methods of forming a field effect transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US07329924B2
公开(公告)日：2008-02-12
申请号：US11704487
申请日：2007-02-09
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L27/12
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

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